Fei Li

7816946, Oct 19, 2010

Jan 28, 2009

12/360948

Volker Hecht - Barsinghausen, DE
Fei Li - Santa Clara CA, US
Jonathan W. Greene - Palo Alto CA, US

Actel Corporation - Mountain View CA

G06F 7/38
H03K 19/177

326 40, 326 41, 326 46, 326 47

A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.

7932745, Apr 26, 2011

Sep 10, 2010

12/879306

Volker Hecht - Barsinghausen, DE
Fei Li - Santa Clara CA, US
Jonathan W. Greene - Palo Alto CA, US

Actel Corporation - Mountain View CA

G06F 7/38
H03K 19/177

326 40, 326 38, 326 39

A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.

20220382945, Dec 1, 2022

May 10, 2022

17/740644

- Chandler AZ, US
Gabriel Barajas - Mountain View CA, US
Fei Li - San Jose CA, US
Hassan Hassan - Waterloo, CA
James Sumit Tandon - Fremont CA, US

Microchip Technology Inc. - Chandler AZ

G06F 30/347

A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.

20210271312, Sep 2, 2021

May 20, 2021

17/326106

- Santa Clara CA, US
Tezaswi Raja - San Jose CA, US
Fei Li - Campbell CA, US
Wen Yueh - San Jose CA, US

G06F 1/3287
G06F 1/3234
G06F 1/3296

Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.

20210089112, Mar 25, 2021

Dec 8, 2020

17/115614

- Santa Clara CA, US
Tezaswi Raja - San Jose CA, US
Fei Li - Campbell CA, US
Wen Yueh - San Jose CA, US

G06F 1/3287

Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.

20190369710, Dec 5, 2019

Jun 1, 2018

15/996334

- Santa Clara CA, US
Tezaswi Raja - Santa Clara CA, US
Fei Li - Santa Clara CA, US
Wen Yueh - Santa Clara CA, US

G06F 1/32

Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.

20190361691, Nov 28, 2019

Aug 12, 2019

16/538265

- Mountain View CA, US
Jing Wang - Santa Clara CA, US
Steve Swan - Los Altos Hills CA, US
Victor Kasatkin - Mountain View CA, US
Fei Li - San Jose CA, US
Zhe Liu - Sunnyvale CA, US
Alex Valle - Daly City CA, US
Peng Tang - San Jose CA, US

G06F 8/60
G06N 20/00

The present disclosure is directed to a technique to reduce latency in feedback-based system performance determination. A system receives, from an application developer device, indications of an in-application event and a first input value for an application content delivery profile. The system receives, via an interface from an application developed by an application developer and executed by a computing device remote from the data processing system and different from the application developer device, a ping indicative of an occurrence of the in-application event on the computing device. The system merges data from the ping with internal data determined by the data processing system to generate merged data. The system determines a predicted performance for the in-application event and provides an indication of the predicted performance. The system configures, responsive to the indication of the predicted performance, the application content delivery profile with a second input value.

20190190522, Jun 20, 2019

Oct 31, 2018

16/177244

- San Jose CA, US
Fei Li - San Jose CA, US

Microsemi SoC Corp. - San Jose CA

H03K 19/177
G06F 7/544

An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.