Yunqiu Wan Phones & Addresses
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3779 Nathan Way, Palo Alto, CA 94303
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3804 Nathan Way, Palo Alto, CA 94303
Publications
Us Patents
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View pageUS Patent:
7369447, May 6, 2008
Filed:
Sep 5, 2006
Appl. No.:
11/515629
Inventors:
Benjamin Louie - Fremont CA, US
Yunqiu Wan - Mountain View CA, US
Aaron Yip - Santa Clara CA, US
Jin-Man Han - Santa Clara CA, US
Yunqiu Wan - Mountain View CA, US
Aaron Yip - Santa Clara CA, US
Jin-Man Han - Santa Clara CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 7/00
US Classification:
36518905, 36523005
Abstract:
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.
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View pageUS Patent:
20060245270, Nov 2, 2006
Filed:
Apr 27, 2005
Appl. No.:
11/115489
Inventors:
Benjamin Louie - Fremont CA, US
Yunqiu Wan - Mountain View CA, US
Aaron Yip - Santa Clara CA, US
Jin-Man Han - Santa Clara CA, US
Yunqiu Wan - Mountain View CA, US
Aaron Yip - Santa Clara CA, US
Jin-Man Han - Santa Clara CA, US
International Classification:
G11C 7/10
US Classification:
365189050
Abstract:
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.