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Bin Wan

from Round Rock, TX
Age ~52
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Also known as:
Leng Bing, Bing L Leng, Wan Bin
Related to:
Yonghua WanLeng BingBing Leng, 91Yuhua Leng, 78Yuhua LengWan LengBing Leng, 51Leng Bing, 50
Connected to:
Aaron Wan, 41Adrian Wan, 36Angel Wan, 70Benjamin T Wan, 65Chea Wan, 52Cheng H Wan, 61Chien M Wan, 70Choo S Wan, 80Christine H Wan, 51Diane Wan, 53

Bin Wan Phones & Addresses

  • Round Rock, TX
  • Temple, TX
  • Sugar Land, TX
  • Houston, TX
  • Cherry Hill, NJ
  • Richmond, CA
  • Hercules, CA
  • Salt Lake City, UT

Resumes

Resumes

Bin Wan Photo 1

Principal Process Engineer

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Location:
14135 southeast Mill Plain Blvd, Vancouver, WA 98684
Industry:
Oil & Energy
Work:
Bright Clear 2016 - 2017
Engineering Consultant
China Merchants Heavy Industry 2016 - 2017
Principal Process Engineer
Chevron Mar 2013 - Jun 2016
Process Engineering Lead at Chevron
Chevron Apr 2012 - Mar 2013
Process Engineer
Chevron Aug 2007 - May 2012
Process Simulation Engineer
Education:
University of Utah 2001 - 2005
Doctorates, Doctor of Philosophy, Chemical Engineering, Philosophy
Skills:
Process Simulation
Engineering
Process Engineering
Upstream
Aspen Hysys
Petroleum
Process Design
P&Id
Cfd
Chemical Engineering
Petrochemical
Feed
Project Engineering
Subsea Engineering
Offshore Drilling
Offshore Process
Energy
Oil and Gas
Gas
Computational Fluid Dynamics
Bin Wan Photo 2

Bin Wan

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Skills:
Microsoft Office
Microsoft Excel
Management
Microsoft Word

Publications

Us Patents

Duty Cycle Measurement For Various Signals Throughout An Integrated Circuit Device

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US Patent:
7895005, Feb 22, 2011
Filed:
Nov 20, 2007
Appl. No.:
11/942966
Inventors:
David W. Boerstler - Round Rock TX, US
Eskinder Hailu - Austin TX, US
Masaaki Kaneko - Round Rock TX, US
Jieming Qi - Austin TX, US
Bin Wan - Pittsburgh PA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 13/00
US Classification:
702 66, 702 79, 702 89, 702107, 702125, 702176, 702178, 327174, 327175
Abstract:
A mechanism is provided for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Absolute Duty Cycle Measurement

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US Patent:
7904264, Mar 8, 2011
Filed:
Nov 12, 2007
Appl. No.:
11/938456
Inventors:
David W. Boerstler - Round Rock TX, US
Eskinder Hailu - Austin TX, US
Masaaki Kaneko - Round Rock TX, US
Jieming Qi - Austin TX, US
Bin Wan - Pittsburgh PA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 35/00
G01R 15/00
US Classification:
702 79, 702 57, 702 85, 702 89, 327175, 327176
Abstract:
A mechanism for measuring the absolute duty cycle of a signal is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.

Structure For A Duty Cycle Measurement Circuit

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US Patent:
7917318, Mar 29, 2011
Filed:
May 30, 2008
Appl. No.:
12/129980
Inventors:
David W. Boerstler - Round Rock TX, US
Eskinder Hailu - Sunnyvale CA, US
Masaaki Kaneko - Round Rock TX, US
Jieming Qi - Austin TX, US
Bin Wan - Pittsburgh PA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 13/00
US Classification:
702 66, 702 79, 702 89, 702107, 702125, 702176, 702178, 327174, 327175
Abstract:
A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Structure For An Absolute Duty Cycle Measurement Circuit

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US Patent:
8032850, Oct 4, 2011
Filed:
May 30, 2008
Appl. No.:
12/129945
Inventors:
David W. Boerstler - Round Rock TX, US
Eskinder Hailu - Sunnyvale CA, US
Masaaki Kaneko - Round Rock TX, US
Jieming Qi - Austin TX, US
Bin Wan - Pittsburgh PA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G01R 23/00
G01R 29/26
US Classification:
716113, 716118, 716119, 716126, 716129, 716130, 716132, 716134, 716136, 716139, 702 72, 702 75, 702 79
Abstract:
A design structure for a circuit for measuring the absolute duty cycle of a signal, is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.

Method And Apparatus For Measuring The Relative Duty Cycle Of A Clock Signal

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US Patent:
7363178, Apr 22, 2008
Filed:
Oct 31, 2006
Appl. No.:
11/555018
Inventors:
David William Boerstler - Round Rock TX, US
Eskinder Hailu - Austin TX, US
Jieming Qi - Austin TX, US
Bin Wan - Pittsburgh PA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 29/02
US Classification:
702 79
Abstract:
In one embodiment, the disclosed methodology and apparatus measure relative duty cycle information of a clock signal with respect to an input node as the clock signal travels to selected nodes of a clock distribution network on an electronic circuit. The apparatus operates in a benchmark mode to determine benchmark duty cycle information and then subsequently operates an a relative mode to determine relative duty cycle information of the clock signal at a selected node in comparison to the clock signal at an external input node.
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Bin Wan from Round Rock, TX, age ~52 Get Report