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Yingxuan Te Li

from Saratoga, CA
Age ~61

Yingxuan Li Phones & Addresses

  • 14091 Elvira St, Saratoga, CA 95070
  • Elk Grove, CA
  • Las Vegas, NV
  • Cupertino, CA
  • Santa Clara, CA
  • San Jose, CA
  • Sacramento, CA

Education

Degree: High school graduate or higher

Publications

Us Patents

Reconfigurable Dual-Mode Multiple Stage Operational Amplifiers

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US Patent:
6522199, Feb 18, 2003
Filed:
May 18, 2001
Appl. No.:
09/861246
Inventors:
Stefanos Sidiropoulos - Palo Alto CA
Yingxuan Li - Cupertino CA
Assignee:
Rambus, Inc. - Los Altos CA
International Classification:
H03F 345
US Classification:
330253, 330292, 330 9
Abstract:
A reconfigurable dual-mode multiple stage operational amplifier circuit includes a configurable portion that can be selectively configured to operate in either a one-pole mode or a two-pole mode. Different exemplary operational amplifier circuits are provided, some of which employ a compensation portion that can be selectively coupled to the configurable portion. For example, in the one-pole operating mode the compensation portion is decoupled from an output of the configurable portion. Conversely, in the two-pole operating mode the compensation portion is coupled to the output. The compensation portion is configured to stabilize a signal on the output. The configurable portion switches between operational modes in response to at least one control signal. The operational amplifier may include a pulse generating portion that is coupled to operatively control the configurable portion in response to the at least one control signal. Such an implementation negates the need for a compensation portion.

Duty Cycle Integrator With Tracking Common Mode Feedback Control

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US Patent:
6573779, Jun 3, 2003
Filed:
May 25, 2001
Appl. No.:
09/865615
Inventors:
Stefanos Sidiropoulos - Palo Alto CA
Yingxuan Li - Cupertino CA
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
G06F 764
US Classification:
327345, 330260
Abstract:
Disclosed herein is a process-tracking clock duty cycle integrator. Common mode feedback is used to set a common mode output voltage that varies with the voltage threshold of MOS elements that implement the circuit. In addition, a buffer is used to control the common mode input voltage to the differential amplifier circuit, and to vary the common mode input voltage with the voltage threshold.

Current-Mode Bus Line Driver Having Increased Output Impedance

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US Patent:
6618786, Sep 9, 2003
Filed:
Aug 28, 2000
Appl. No.:
09/650430
Inventors:
Stefanos Sidiropoulos - Palo Alto CA
Yingxuan Li - Cupertino CA
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
G06F 1314
US Classification:
710305, 326 86
Abstract:
A current-mode bus line driver includes a primary current source and a supplemental current source. The primary current source is an open-drain NMOS transistor, whose output current decreases at low output voltages. The supplemental current source is responsive to low output voltages to provide a supplemental output current, in addition to the output current of the primary current source. The supplemental current source consists of an inverter and a current mirror. The inverter produces a correction current that is inversely related to the voltage output of the primary current source. This correction current is amplified by the current mirror to produce the supplemental output current. The current mirror is self-limiting, in that its current output falls off at very low output voltages.

Circuit, Apparatus And Method For Improved Current Distribution Of Output Drivers Enabling Improved Calibration Efficiency And Accuracy

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US Patent:
6674377, Jan 6, 2004
Filed:
Apr 25, 2002
Appl. No.:
10/132246
Inventors:
Yingxuan Li - Cupertino CA
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H03M 110
US Classification:
341120, 341118, 341144, 341145
Abstract:
A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (âDACâ) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N. According to an embodiment of the present invention, the circuit is in a memory device and a controller generates calibration signals.

Dual Loop Phase Lock Loops Using Dual Voltage Supply Regulators

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US Patent:
6809600, Oct 26, 2004
Filed:
Jan 3, 2003
Appl. No.:
10/336570
Inventors:
Kun-Yung Ken Chang - Los Altos CA
Yingxuan Li - Cupertino CA
Stefanos Sidiropoulos - Palo Alto CA
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H03L 700
US Classification:
331 17, 331 10, 331 1 A
Abstract:
Dual loop phase lock loops having a high loop bandwidth with low power consumption are described. Each loop is provided with a voltage supply regulator circuit which regulates the voltage of a portion of each loop. In one embodiment, the outer loop employs a regulation circuit comprising a two stage operational amplifier which is compensated by a compensation circuit that is configured to ensure that the dominant pole of the operational amplifier is associated with the first stage of the operational amplifier.

Circuit, Architecture And Method For Tracking Loop Bandwidth In A Frequency Synthesizer Having A Wide Frequency Range

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US Patent:
6850124, Feb 1, 2005
Filed:
Jun 17, 2003
Appl. No.:
10/464278
Inventors:
Yingxuan Li - Cupertino CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H03B 2700
H03L 700
US Classification:
331 57, 331 17, 331 34
Abstract:
Circuits, architectures, and methods for tracking a phase locked loop (PLL) configuration such that its VCO gain is essentially a linear function of its feedback divider factor over a wide frequency range. The circuit generally includes an oscillator loop having (2+1) stages, where n is an integer of at least 1, and at least three of the stages comprise a delay circuit and a characteristic control circuit configured to (i) receive divider information and (ii) set or change a delay characteristic of the delay circuit in response to the divider information. The architectures generally relate to PLLs that include a circuit embodying one or more of the inventive concepts disclosed herein. The method generally includes the steps of generating a periodic signal from an oscillator, dividing the periodic signal by a first number, and setting a characteristic property of at least part of the oscillator in accordance with the first number. The present invention advantageously tracks changes to a PLL and adjusts the VCO gain dynamically and in a predictable and controllable manner in response to such changes. The present invention avoids noisy and/or complicated charge pump and/or filter designs, and advantageously improves PLL stability, reliability and/or performance.

Circuit, Apparatus And Method For Improved Current Distribution Of Output Drivers Enabling Improved Calibration Efficiency And Accuracy

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US Patent:
6909387, Jun 21, 2005
Filed:
Oct 28, 2003
Appl. No.:
10/695569
Inventors:
Yingxuan Li - Cupertino CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H03M001/10
US Classification:
341120, 341118, 341144
Abstract:
A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (“DAC”) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N. According to an embodiment of the present invention, the circuit is in a memory device and a controller generates calibration signals.

Circuit, Apparatus And Method For Improved Current Distribution Of Output Drivers Enabling Improved Calibration Efficiency And Accuracy

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US Patent:
7002500, Feb 21, 2006
Filed:
Apr 26, 2005
Appl. No.:
11/114326
Inventors:
Yingxuan Li - Cupertino CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H03M 1/66
US Classification:
341144, 341145
Abstract:
A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (“DAC”) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N. According to an embodiment of the present invention, the circuit is in a memory device and a controller generates calibration signals.
Yingxuan Te Li from Saratoga, CA, age ~61 Get Report