Search

Yi Jen Su

from Emeryville, CA
Age ~54
Get Report
Also known as:
Yi J Su, Jen Su Yijen, Yijen Jen Su, Ethan Su, Yijen J Su, Jen Su, Su Su Yijen, Jen Su Yi
Phone and address:
6363 Christie Ave, Oakland, CA 94608
(510) 653-7566
Related to:
Shwuyuan L Chen, 70
Connected to:
Baolei Su, 66Beihan Su, 52Bogong Su, 86Bowei Su, 31Bryan J Su, 39Carrie J Su, 39Ching-Hua Su, 70Chunming M Su, 54Danielle Su, 31Daqing S Su, 54

Yi Su Phones & Addresses

  • 6363 Christie Ave, Emeryville, CA 94608 (510) 653-7566 (510) 654-1123
  • San Leandro, CA

Resumes

Resumes

Yi Su Photo 1

Senior Staff Device Design Engineer At Alpha & Omega Semiconductor

View page
Position:
Senior Staff Device Design Engineer at Alpha & Omega Semiconductor, Senior Staff Device Design Engineer at Alpha & Omega Semiconductor
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Alpha & Omega Semiconductor since Dec 2005
Senior Staff Device Design Engineer
Louisiana Tech University Feb 2002 - Dec 2005
Assistant Professor
Education:
Southampton University 1994 - 1997
PhD, Microelectronics
Yi Su Photo 2

Yi Su

View page
Yi Su Photo 3

Yi Su

View page
Yi Su Photo 4

Yi Su

View page
Yi Su Photo 5

Senior Engineer At Qualcomm

View page
Position:
Senior Engineer at Qualcomm
Location:
San Francisco Bay Area
Industry:
Wireless
Work:
Qualcomm since Jul 2010
Senior Engineer
Qualcomm Jun 2009 - Sep 2009
Intern
Education:
University of California, Los Angeles 2006 - 2010
Ph.D., Electrical Engineering Tsinghua University 2000 - 2006
BS, MS, Electronic Engineering
Yi Su Photo 6

Yi Su

View page
Work:
Chairman of Department
2009 to 2010
Haier Pharmacy

Dec 2008 to Feb 2009
Internship
Education:
College of Chemical Engineering University of Florida
Sep 2011
Master in Engineering
School of Pharmaceutical Science Shandong University
Sep 2007 to Jul 2011
B.S.

Business Records

Name / Title
Company / Classification
Phones & Addresses
Yi Su
President
SBE, INC
Nonclassifiable Establishments
249 W Jackson St #558, Hayward, CA 94544
Yi Su
President
BCMC, INC
23785 Cabot Blvd #318, Hayward, CA 94545
Yi Su
President
SUPERIOR BUILDING ENGINEERING, INC
23785 Cabot Blvd STE 318, Hayward, CA 94545
Yi Su
President, Principal
HOMES WAREHOUSE, INC
Ret Misc Merchandise · Reupholstery & Furniture Repair
1765 Landness Ave #222, Milpitas, CA 95035
1765 Landess Ave, Milpitas, CA 95035
1762 Tyler Ave, El Monte, CA 91733
(626) 350-1808, (626) 350-1808

Publications

Us Patents

Integration Of A Sense Fet Into A Discrete Power Mosfet

View page
US Patent:
7799646, Sep 21, 2010
Filed:
Apr 7, 2008
Appl. No.:
12/098970
Inventors:
Yi Su - Sunnyvale CA, US
Anup Bhalla - Santa Clara CA, US
Daniel Ng - Campbell CA, US
Assignee:
Alpha & Omega Semiconductor, Ltd - Hamilton
International Classification:
H01L 21/336
US Classification:
438284, 438286
Abstract:
A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.

Reduced Mask Configuration For Power Mosfets With Electrostatic Discharge (Esd) Circuit Protection

View page
US Patent:
7825431, Nov 2, 2010
Filed:
Dec 31, 2007
Appl. No.:
12/006398
Inventors:
Anup Bhalla - Santa Clara CA, US
Xiaobin Wang - San Jose CA, US
Wei Wang - Santa Clara CA, US
Yi Su - Sunnyvale CA, US
Daniel Ng - Campbell CA, US
Assignee:
Alpha & Omega Semicondictor, Ltd.
International Classification:
H01L 29/72
H01L 23/62
US Classification:
257173, 257355, 257E29008, 257E29015
Abstract:
A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

Configuration Of Gate To Drain (Gd) Clamp And Esd Protection Circuit For Power Device Breakdown Protection

View page
US Patent:
7902604, Mar 8, 2011
Filed:
Feb 9, 2009
Appl. No.:
12/378039
Inventors:
Yi Su - Sunnyvale CA, US
Anup Bhalla - Santa Clara CA, US
Daniel Ng - Campbell CA, US
Assignee:
Alpha & Omega Semiconductor, Inc. - Sunnyvale CA
International Classification:
H01L 23/62
US Classification:
257356, 257551
Abstract:
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.

Integration Of Sense Fet Into Discrete Power Mosfet

View page
US Patent:
7939882, May 10, 2011
Filed:
Aug 27, 2010
Appl. No.:
12/870489
Inventors:
Yi Su - Sunnyvale CA, US
Anup Bhalla - Santa Clara CA, US
Assignee:
Alpha and Omega Semiconductor Incorporated - Sunnyvale CA
International Classification:
H01L 29/66
US Classification:
257328, 438212
Abstract:
A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs. A transistor portion of the sense FET is surrounded by transistors of the main FET. An electrical isolation structure that surrounds the main FET is configured to electrically isolate source and body regions of the main FET from source and body regions of the sense FET. A sense FET source pad is located at an edge of the main FET and spaced apart from the transistor portion of the sense FET. The sense FET source pad is connected to the transistor portion of the sense FET by a sense FET probe metal. The isolation structure is configured such that the transistor portion of the sense FET and the sense FET source pad are located outside an active area of the main FET.

Integration Of A Sense Fet Into A Discrete Power Mosfet

View page
US Patent:
7952144, May 31, 2011
Filed:
Aug 20, 2010
Appl. No.:
12/860777
Inventors:
Yi Su - Sunnyvale CA, US
Anup Bhalla - Santa Clara CA, US
Daniel Ng - Campbell CA, US
Assignee:
Alpha & Omega Semiconductor, Ltd - Hamilton
International Classification:
H01L 29/66
US Classification:
257341, 257288
Abstract:
A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.

Layouts For Multiple-Stage Esd Protection Circuits For Integrating With Semiconductor Power Device

View page
US Patent:
8053808, Nov 8, 2011
Filed:
May 21, 2007
Appl. No.:
11/804906
Inventors:
Yi Su - Sunnyvale CA, US
Anup Bhalla - Santa Clara CA, US
Daniel Ng - Campbell CA, US
Wei Wang - Santa Clara CA, US
Ji Pan - Santa Clara CA, US
Assignee:
Alpha & Omega Semiconductor, Ltd.
International Classification:
H01L 29/66
US Classification:
257173, 257355, 257356, 257E21355, 257E21356, 438140, 438141
Abstract:
A semiconductor power device supported on a semiconductor substrate includes a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a source metal connected to the source region, and a gate metal configured as a metal stripe surrounding a peripheral region of the substrate connected to a gate pad wherein the gate metal and the gate pad are separated from the source metal by a metal gap. The semiconductor power device further includes an ESD protection circuit includes a plurality of doped polysilicon regions of opposite conductivity types constituting ESD diodes extending across the metal gap and connected between the gate metal and the source metal on the peripheral region of the substrate.

Multi-Die Package

View page
US Patent:
8164199, Apr 24, 2012
Filed:
Jul 31, 2009
Appl. No.:
12/534057
Inventors:
Anup Bhalla - Santa Clara CA, US
Yi Su - Sunnyvale CA, US
David Grey - Santa Clara CA, US
Assignee:
Alpha and Omega Semiconductor Incorporation - Sunnyvale CA
International Classification:
H01L 23/495
H01L 23/02
H01L 29/40
US Classification:
257777, 257666, 257686
Abstract:
A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die.

Integration Of A Sense Fet Into A Discrete Power Mosfet

View page
US Patent:
8304315, Nov 6, 2012
Filed:
May 31, 2011
Appl. No.:
13/149051
Inventors:
Yi Su - Sunnyvale CA, US
Anup Bhalla - Santa Clara CA, US
Daniel Ng - Campbell CA, US
Assignee:
Alpha and Omega Semiconductor Incorporated - Sunnyvale CA
International Classification:
H01L 21/336
US Classification:
438270, 257341
Abstract:
A main FET and one or more sense FETs are formed in a common substrate. The main FET and sense FET(s) include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and sense FET(s). An electrical isolation may be between the gate terminals of the main FET and the sense FET(s). A sense pad in electrical contact with the source of the one or more sense FETs does not overlap an area of the device containing the sense FET(s). It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
Control profile
Yi Jen Su from Emeryville, CA, age ~54 Get Report