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Venkata S Rangavajjhala

from Fremont, CA
Age ~57
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Also known as:
Venkata Te Rangavajjhala, Venkata Balaraman Anita Rangavajjhala, Venkat Rangavajjhala, Venkata A
Phone and address:
141 Black Mountain Cir, Fremont, CA 94536
(510) 790-8390
Related to:
Jaya Balaraman, 73Anita Balaraman, 51Balaraman Venketaraman, 84Sujatha Balaraman, 50R RangavajjhalaApparna Balaraman, 44Ramasesha Rangavajjhala
Connected to:
Shirley T Rangaves, 87Prakash B Rangavittal, 49Abhijeet P Rangdal, 43Amanda M Range, 38Ellen E Range, 44Grace E Range, 98Howard A Range, 45Jennifer L Range, 56Luke T Range, 38Melanie E Range, 37

Venkata Rangavajjhala Phones & Addresses

  • 141 Black Mountain Cir, Fremont, CA 94536 (510) 790-8390
  • 146 Celada Ct, Fremont, CA 94539 (510) 445-1665
  • 39224 Guardino Dr, Fremont, CA 94538 (510) 796-6392
  • 39887 Cedar Blvd, Newark, CA 94560
  • Napa, CA
  • Milpitas, CA
  • Alameda, CA
  • 146 Celada Ct, Fremont, CA 94539 (510) 220-4476

Work

Position: Administrative Support Occupations, Including Clerical Occupations

Education

Degree: Associate degree or higher

Resumes

Resumes

Venkata Rangavajjhala Photo 1

Director

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Location:
146 Celada Ct, Fremont, CA 94539
Industry:
Telecommunications
Work:
Juniper Networks
Director
Tellabs Jul 2004 - Dec 2007
Asic Design Manager
Ciena Feb 1999 - Apr 2004
Asic Design Manager
Neomagic Jul 1997 - Feb 1999
Senior Asic Engineer
Arcus/Armedia Feb 1996 - Jun 1997
Senior Member of Technical Staff
Education:
Vanderbilt University 1988 - 1990
Master of Science, Masters, Electrical Engineering Indian Institute of Technology, Madras 1984 - 1988
Skills:
Asic
Embedded Systems
Eda
Ethernet
Ic
Hardware
Soc
Debugging
Mpeg
Fpga
Rtl Design
Verilog
Switching
Hardware Architecture
Interests:
Science and Technology
Education
Environment
Economic Empowerment
Languages:
English
Venkata Rangavajjhala Photo 2

Venkata Rangavajjhala

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Publications

Us Patents

Method And Apparatus For Providing Non-Power-Of-Two Even Count Gray Code

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US Patent:
7796062, Sep 14, 2010
Filed:
Oct 17, 2007
Appl. No.:
11/874077
Inventors:
Venkata Rangavajjhala - Fremont CA, US
Naveen K. Jain - San Jose CA, US
Assignee:
Tellabs San Jose, Inc. - Naperville IL
International Classification:
H03M 7/16
US Classification:
341 96, 711218
Abstract:
An apparatus and a method for enhancing digital processing implementation using non-power-of-two even count Gray coding are disclosed. The even count encoding device includes a first circuit, a second circuit, and a coding circuit. The first circuit, in one embodiment, is configured to identify a first portion of entries in a table in response to an input number. The second circuit is capable of determining a second portion of entries in the table in response to the input number, wherein the number of the first portion of entries and the number of the second portion of the entries are substantially the same. The coding circuit is operable to concatenate the second portion of the entries to the first portion of the entries to form an output table, which includes a sequence of even count integers wherein the difference between two adjacent integers is one bit position.

Method And Apparatus For Providing Line Rate Netflow Statistics Gathering

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US Patent:
7855967, Dec 21, 2010
Filed:
Sep 26, 2008
Appl. No.:
12/239041
Inventors:
Venkata Rangavajjhala - Fremont CA, US
Marc A. Schaub - Sunnyvale CA, US
Assignee:
Tellabs San Jose, Inc. - Naperville IL
International Classification:
H04J 1/16
H04J 3/14
G06F 13/28
G06F 15/173
US Classification:
370241, 370252, 370253, 370255, 709224, 709226, 710 22
Abstract:
An apparatus and method for using a direct memory access (“DMA”) to facilitate netflow statistics are disclosed. A network device such as a router or a switch, in one embodiment, includes a statistic component, a local memory, and a memory access controller. The statistic component is configured to gather information relating to net usage from packet flows or netflows in response to corresponding index values or tags. While the local memory such as a cache provides the index values or tags assignable to packet flows, the memory access controller such as a DMA transfers at least a portion of the index values or tags between the local memory and a main memory for enhancing capacity of the local memory.

Method And Apparatus For A Graceful Flow Control Mechanism In A Tdm-Based Packet Processing Architecture

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US Patent:
8072882, Dec 6, 2011
Filed:
Jan 23, 2009
Appl. No.:
12/358865
Inventors:
Naveen K. Jain - San Jose CA, US
Venkata Rangavajjhala - Fremont CA, US
Assignee:
Tellabs San Jose, Inc. - Naperville IL
International Classification:
H04L 12/26
G06F 15/16
G06F 13/24
US Classification:
370230, 709230, 710260
Abstract:
A method and apparatus for improving packet processing employing a network flow control mechanism are disclosed. A network process, in one embodiment, suspends distribution of incoming packet(s) to one or more, packet processing engines (“PEs”) upon detecting a stalling request. After identifying currently executing operations initiated by one or more kicking circuits before the issuance of stalling request, the process allows the currently executing operations to complete despite the activation of the stalling request.

Method And Apparatus For Improving Packet Processing Performance Using Multiple Contexts

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US Patent:
8072974, Dec 6, 2011
Filed:
Jul 18, 2008
Appl. No.:
12/175702
Inventors:
Naveen K. Jain - San Jose CA, US
Venkata Rangavajjhala - Fremont CA, US
Assignee:
Tellabs San Jose Inc - Naperville IL
International Classification:
H04L 12/56
US Classification:
370389
Abstract:
A network processing device having multiple processing engines capable of providing multi-context parallel processing is disclosed. The device includes a receiver and a packet processor, wherein the receiver is capable of receiving packets at a predefined packet flow rate. The packet processor, in one embodiment, includes multiple processing engines, wherein each processing engine is further configured to include multiple context processing components. The context processing components are used to provide multi-context parallel processing to increase throughput.

Processing System Having Multiple Engines Connected In A Daisy Chain Configuration

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US Patent:
8074054, Dec 6, 2011
Filed:
Dec 12, 2007
Appl. No.:
11/954718
Inventors:
Venkata Rangavajjhala - Fremont CA, US
Naveen K. Jain - San Jose CA, US
Assignee:
Tellabs San Jose, Inc. - Naperville IL
International Classification:
G06F 15/00
G06F 15/76
US Classification:
712 28, 712 29, 712 30
Abstract:
A processing system includes a group of processing units (“PUs”) arranged in a daisy chain configuration or a sequence capable of parallel processing. The processing system, in one embodiment, includes PUs, a demultiplexer (“demux”), and a multiplexer (“mux”). The PUs are connected or linked in a sequence or a daisy chain configuration wherein a first PU is located at the beginning of the sequence and a last digital PU is located at the end of the sequence. Each PU is configured to read an input data packet from a packet stream during a designated reading time frame. If the time frame is outside of the designated reading time frame, a PU allows a packet stream to pass through. The demux forwards a packet stream to the first digital processing unit. The mux receives a packet steam from the last digital processing unit.

Method And Apparatus For Network Load Balancing Using Indirection Ram During Classification

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US Patent:
8169915, May 1, 2012
Filed:
Sep 26, 2008
Appl. No.:
12/239118
Inventors:
Venkata Rangavajjhala - Fremont CA, US
Marc A. Schaub - Sunnyvale CA, US
Assignee:
Tellabs Operations, Inc. - Naperville IL
International Classification:
H04J 1/16
US Classification:
370237, 370378, 37039532
Abstract:
An apparatus and a method for load balancing across multiple routes using an indirection table and hash function during a process of packet classification are disclosed. A network device such as a router includes a memory, a hash component, and a result memory. The memory is referred to as an indirection random access memory (“RAM”), is capable of storing information regarding number of paths from source devices to destination devices. The memory, in one embodiment, provides a base index value and a range number indicating the number of paths associated with the base index value. The hash component generates a hash index in response to the base index value and the range number. Upon generation of hash index, the result memory identifies a classification result in response to the hash index.

Method And Apparatus For Improving Performance Of Tdm Sequencing For Packet Processing Engines Using A Delay Line

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US Patent:
8179887, May 15, 2012
Filed:
Feb 1, 2008
Appl. No.:
12/024806
Inventors:
Naveen K. Jain - San Jose CA, US
Venkata Rangavajjhala - Fremont CA, US
Assignee:
Tellabs Operations, Inc. - Naperville IL
International Classification:
H04Q 11/04
US Classification:
370366, 370383
Abstract:
A network system, having an array of processing engines (“PEs”) and a delay line, improves packet processing performance for time division multiplexing (“TDM”) sequencing of PEs. The system includes an ingress circuit, a delay line, a demultiplexer, a tag memory, and a multiplexer. After the ingress circuit receives a packet from an input port, the delay line stores the packet together with a unique tag value. The delay line, in one embodiment, provides a predefined time delay for the packet. Once the demultiplexer forwards the packet to an array of PEs for packet processing, a tag memory stores the tag value indexed by PE number. The PE number identifies a PE in the array, which was assigned to process the packet. The multiplexer is capable of multiplex packets from PE array and replacing the packet with the processed packet in the delay line in response to the tag value.

Method And Apparatus For Measuring System Latency Using Global Time Stamp

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US Patent:
8228923, Jul 24, 2012
Filed:
Jan 9, 2008
Appl. No.:
11/971427
Inventors:
Naveen K. Jain - San Jose CA, US
Venkata Rangavajjhala - Fremont CA, US
Assignee:
Tellabs Operations, Inc. - Naperville IL
International Classification:
H04L 12/28
H04L 12/56
H04J 3/06
H04J 3/00
US Classification:
37039562, 370350, 370503, 370509, 370510, 370511, 370512
Abstract:
A network device having a system performance measurement unit employing one or more global time stamps for measuring the device performance is disclosed. The device includes an ingress circuit, a global time counter, an egress circuit, and a processor. The ingress circuit is configured to receive a packet from an input port while the global time counter generates an arrival time stamp in accordance with the arrival time of the packet. The egress circuit is capable of forwarding the packet to other network devices via an output port. The processor, in one embodiment, is configured to calculate packet latency in response to the arrival time stamp.
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Venkata S Rangavajjhala from Fremont, CA, age ~57 Get Report