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Vamsi K Paidi

from Irvine, CA
Age ~45
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Also known as:
Vamsi Krishnachaitanya Paidi, Vamsi Q Paidi, Aidil P Vamsi, Paidi Vamsi
Phone and address:
30 Royal Victoria, Irvine, CA 92606
Connected to:
Perry M Paielli, 68Luc Paiement, 65George I Paier, 62Annemarie C Paiga, 53Joan E Paiga, 84Adam M Paige, 50Alden Paige, 32Alison Paige, 60Althea R Paige, 102Alyssia Paige, 33

Vamsi Paidi Phones & Addresses

  • 30 Royal Victoria, Irvine, CA 92606
  • 2812 Hope Ave, Carlsbad, CA 92008
  • 2803 Via Carrio, Carlsbad, CA 92008
  • Oceanside, CA
  • 6667 El Colegio Rd, Goleta, CA 93117
  • 6689 El Colegio Rd, Goleta, CA 93117
  • Santa Barbara, CA

Work

Company: Skyworks solutions, inc. Jul 2004 to Mar 2005 Position: Senior rfic designer

Education

Degree: Master of Science, Doctorates, Masters, Doctor of Philosophy School / High School: Uc Santa Barbara 2000 to 2004

Skills

Semiconductors

Languages

English

Industries

Semiconductors

Resumes

Resumes

Vamsi Paidi Photo 1

Senior Manager, Rf And Ms Ic Design

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Location:
30 Royal Victoria, Irvine, CA 92606
Industry:
Semiconductors
Work:
Skyworks Solutions, Inc. Jul 2004 - Mar 2005
Senior Rfic Designer
Maxlinear Jul 2004 - Mar 2005
Senior Manager, Rf and Ms Ic Design
Education:
Uc Santa Barbara 2000 - 2004
Master of Science, Doctorates, Masters, Doctor of Philosophy Indian Institute of Technology, Madras 1996 - 2000
Government Arts College, Srikakulam, India 1994 - 1996
Government High School, Srikakulam, India 1984 - 1994
Government High School, Srikakulam 1984 - 1994
Skills:
Semiconductors
Languages:
English

Publications

Us Patents

Harmonic Rejection Mixer Architecture With Reduced Sensitivity To Gain And Phase Mismatches

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US Patent:
20120322398, Dec 20, 2012
Filed:
Dec 20, 2011
Appl. No.:
13/331792
Inventors:
Raja Pullela - Carlsbad CA, US
Vamsi Paidi - Carlsbad CA, US
Rahul Bhatia - Carlsbad CA, US
Assignee:
MAXLINEAR, INC. - Carlsbad CA
International Classification:
H04B 1/10
US Classification:
455302
Abstract:
A harmonic rejection mixer includes a first scaling circuit for scaling an RF signal to generate a plurality of scaled RF signals, a first switching stage for sampling the scaled RF signals using a first plurality of switching signals, and a second mixing stage for mixing the sampled RF signals with a second plurality of switching signals to generate a plurality of frequency translated signals having different phases. A combiner adds the frequency translated signals together to generate a first plurality of baseband versions of the RF signal. A first amplifier stage processes the first plurality of baseband versions to generate a second plurality of baseband versions. The mixer further includes a second scaling circuit for scaling the second plurality of baseband versions and a second amplifier stage to generate an in-phase baseband signal and a quadrature baseband signal from the scaled second plurality of baseband versions.

Method And System For Improving Linearity Of An Amplifier By Means Of Im3 Cancelation

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US Patent:
20120306576, Dec 6, 2012
Filed:
May 31, 2012
Appl. No.:
13/485039
Inventors:
Vamsi Paidi - Irvine CA, US
Masoud Koochakzadeh - Vista CA, US
International Classification:
H03F 3/16
US Classification:
330277
Abstract:
An amplifier for providing improved third-order intermodulation (IM3) cancelation. The amplifier may comprise a main branch for amplifying input signals and an auxiliary branch for generating IM3 signals that are equal to corresponding IM3 components resulting from amplifying input signals via the main branch, with both of the main and the auxiliary branches being configured as differential circuits. The differential implementation may result in the auxiliary branch generating IM3 distortion signals with minimal or no non-IM3 signals. Each of the main and the auxiliary branches may comprise at least two transistor elements. Separate bias current sources may be applied to each of the main and the auxiliary branches. Operation of the auxiliary branch may be controlled by adjusting one or both of the bias current sources. Outputs of the main and the auxiliary branches may be cross-coupled, to invert a sign of IM3 distortion signals generated via the auxiliary branch.

Method And System For A Distributed Transmission Line Multiplexer For A Multi-Core Multi-Mode Voltage-Controlled Oscillator (Vco)

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US Patent:
20190280648, Sep 12, 2019
Filed:
Mar 6, 2018
Appl. No.:
15/913127
Inventors:
- Carlsbad CA, US
Sangeetha Gopalakrishnan - Carlsbad CA, US
Raghava Manas Bachu - Carlsbad CA, US
Vamsi Paidi - Carlsbad CA, US
International Classification:
H03B 5/12
H03L 7/24
H03L 5/02
H03H 7/40
Abstract:
Methods and systems for a distributed transmission line multiplexer for a multi-core multi-mode voltage-controlled oscillator (VCO) may comprise a plurality of voltage controlled oscillators (VCOs) arranged adjacent to each other, where each of the plurality of VCOs are operable to generate an output signal at a configurable frequency, an impedance matching circuit comprising a respective driver and impedance matching elements coupled to each of the plurality of VCOs, and an output device coupled to the impedance matching circuit. The impedance matching elements may include capacitors and inductors. Between each adjacent pair of the respective drivers coupled to each of the plurality of VCOs, the impedance matching elements may include two inductors coupled in series between the drivers and a capacitor coupled to ground and to a common node between the two inductors. Impedance values of the capacitors and inductors may be configurable.

Method And System For A Pseudo-Differential Low-Noise Amplifier At Ku-Band

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US Patent:
20190173441, Jun 6, 2019
Filed:
Feb 5, 2019
Appl. No.:
16/268002
Inventors:
- Carlsbad CA, US
Vamsi Paidi - Carlsbad CA, US
International Classification:
H03F 3/45
H03F 1/52
H03F 3/195
Abstract:
Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.

Outdoor Unit Resonator Correction

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US Patent:
20190068227, Feb 28, 2019
Filed:
Oct 26, 2018
Appl. No.:
16/171463
Inventors:
- Carlsbad CA, US
Anand Anandakumar - San Diego CA, US
Stephane Laurent-Michel - Carlsbad CA, US
Sheng Ye - Carlsbad CA, US
Raja Pullela - Irvine CA, US
Glenn Chang - Carlsbad CA, US
Vamsi Paidi - Irvine CA, US
International Classification:
H04B 1/10
Abstract:
A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.

Method And System For A Sampled Loop Filter In A Phase Locked Loop (Pll)

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US Patent:
20180191357, Jul 5, 2018
Filed:
Feb 27, 2018
Appl. No.:
15/906578
Inventors:
- Carlsbad CA, US
Sheng Ye - Carlsbad CA, US
Vamsi Paidi - Carlsbad CA, US
Raghava Manas Bachu - Carlsbad CA, US
International Classification:
H03L 7/085
H03L 7/099
H03L 7/197
H03L 7/093
Abstract:
Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

Configurable, Highly-Integrated Satellite Receiver

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US Patent:
20180191452, Jul 5, 2018
Filed:
Feb 28, 2018
Appl. No.:
15/907404
Inventors:
- Carlsbad CA, US
Raja Pullela - Irvine CA, US
Madhukar Reddy - Carlsbad CA, US
Timothy Gallagher - Encinitas CA, US
Shantha Murthy Prem Swaroop - Irvine CA, US
Curtis Ling - Carlsbad CA, US
Vamsi Paidi - Irvine CA, US
Wenjian Chen - Irvine CA, US
International Classification:
H04H 40/90
H04N 21/61
Abstract:
A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.

Method And System For A Configurable Low-Noise Amplifier With Programmable Band-Selection Filters

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US Patent:
20180159572, Jun 7, 2018
Filed:
Feb 2, 2018
Appl. No.:
15/887605
Inventors:
- Carlsbad CA, US
Wenjian Chen - Carlsbad CA, US
Vamsi Paidi - Carlsbad CA, US
International Classification:
H04B 1/16
H03F 3/195
H03F 1/56
H03F 3/72
Abstract:
Methods and systems for a configurable low-noise amplifier with programmable band-selection filters may comprise a receiver with a low-noise amplifier (LNA) with first and second input terminals and differential output terminals; a low pass filter operably coupled to the LNA; a high pass filter operably coupled to the second input terminal of the LNA; and a signal source input coupled to the low pass filter and the high pass filter. The LNA may be operable to receive signals in a pass band of the high pass filter and a pass band of the low pass filter. The receiver may be operable to amplify input signals in the pass band of a first filter but not signals in the pass band of the second filter by operably coupling the second to ground.
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Vamsi K Paidi from Irvine, CA, age ~45 Get Report