Sudhakar C Pamarti

7650526, Jan 19, 2010

Dec 9, 2005

11/299073

Elad Alon - Saratoga CA, US
Sudhakar Pamarti - Los Angeles CA, US

Rambus Inc. - Los Altos CA

G06F 1/04

713503, 713400

An integrated circuit device is described. The circuit device may include a group of signal nodes, including a first signal node and a second signal node, a transmitter coupled to the group of signal nodes, and a first clock circuit coupled to the transmitter. The transmitter may transmit a first signal on the first signal node and a second signal on the second signal node. The first signal and the second signal may correspond to a first sequence of data bits during a sequence of bit times. The first clock circuit may control a transmit time of at least one of the first signal and the second signal. The first clock circuit may include a first phase adjustment element that provides compensation for a first timing offset between the first signal and the second signal. The first timing offset may be less than a bit time in the sequence of bit times.

8509321, Aug 13, 2013

Dec 23, 2004

11/021514

Elad Alon - Saratoga CA, US
Sudhakar Pamarti - Los Angeles CA, US
Fariborz Assaderaghi - Los Altos CA, US
Kun-Yung Chang - Los Altos CA, US

Rambus Inc. - Sunnyvale CA

H04K 1/10

375260, 375267, 375290, 375295

A memory system with a simultaneous bi-directional link includes a controller, a memory device and a set of signal lines coupled to the controller and the memory device. Simultaneous communication between the controller and the memory device on the set of signal lines uses a first band of frequencies, and between the memory device and the controller on the set of signal lines uses a second band of frequencies. The controller is configured to dynamically adjust the first band of frequencies based on a predetermined data rate between the controller and the memory device and to dynamically adjust the second band of frequencies based on a predetermined data rate between the memory device and the controller.

20060018344, Jan 26, 2006

Jul 21, 2004

10/899720

Sudhakar Pamarti - Mountain View CA, US

H04J 1/00

370480000, 370535000, 370366000

A high-speed communications system utilizes approximate bit-loading during data transmission in a channel. In one embodiment, a plurality of parallel data preparation circuits in a data transmission circuit receive respective subsets of a data stream, each of the respective subsets of the data stream having a data rate that is less than a data rate of the data stream. Converters in the data preparation circuits convert the respective subsets of the data stream into respective analog signals. Multipliers in the data preparation circuits multiply the respective analog signals by respective vectors to produce respective sub-channel signals. At least a frequency band in the spectrum corresponding to one of the respective sub-channel signals partially overlaps at least a frequency band for at least one other of the respective sub-channel signals. The respective sub-channel signals are combined prior to transmission.

20070132485, Jun 14, 2007

Dec 9, 2005

11/299072

Elad Alon - Saratoga CA, US
Sudhakar Pamarti - Los Angeles CA, US

H03K 5/19

327018000

A signaling device is described. The signaling device may include a group of four signal nodes, four differential receivers and a logic circuit. The group of four signal nodes may receive a sequence of data bits during a sequence of bit times. A respective differential receiver of the four differential receivers may be coupled to two respective signal nodes in the group of four signal nodes. The logic circuit may extract common-mode data from signals on the group of four signal nodes using outputs from the four differential receivers such that three data bits are received on the group of four signal nodes during each bit time of the sequence of bit times.

20120063291, Mar 15, 2012

Sep 9, 2010

12/878547

Tzu-Chien Hsueh - Hillsboro OR, US
Sudhakar Pamarti - Los Angeles CA, US

THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA

H04J 13/02

370201

Synchronous CDMA/spread spectrum methods, devices, and systems are used to suppress crosstalk in clock-forwarded on-chip interconnects. Transmitting a spread spectrum signal across on-chip interconnects for recovery at the terminus permit integrated chip designers to overcome the effects of capacitive cross-talk between adjacent data bus lines. The methods, devices, and systems provided herein improve cross-talk immunity between adjacent high speed signal lines by applying synchronous CDMA spread spectrum techniques to some or all of the high speed signal lines. Other methods, devices, and systems provided herein apply synchronous CDMA spread spectrum techniques to the concept of sending phantom signals to reduce the number of signal lines used to carry data.

20140321257, Oct 30, 2014

Jul 7, 2014

14/324291

- Oakland CA, US
Sudhakar Pamarti - Los Angeles CA, US

H04B 1/7103

370201

Synchronous CDMA/spread spectrum methods, devices, and systems are used to suppress crosstalk in clock-forwarded on-chip interconnects. Transmitting a spread spectrum signal across on-chip interconnects for recovery at the terminus permit integrated chip designers to overcome the effects of capacitive cross-talk between adjacent data bus lines. The methods, devices, and systems provided herein improve cross-talk immunity between adjacent high speed signal lines by applying synchronous CDMA spread spectrum techniques to some or all of the high speed signal lines. Other methods, devices, and systems provided herein apply synchronous CDMA spread spectrum techniques to the concept of sending phantom signals to reduce the number of signal lines used to carry data.