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Srinivasan R Iyengar

from Fremont, CA
Age ~59
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Also known as:
Srinivasa R Iyengar, Srinivasan R Srinivasan, Sriniva Iyengar, Sirnivasan Iyengar, Rajagopal Srinivasan, Iyengar Srinivasan, Rajagopal Iyengar Srinivasan
Phone and address:
5375 Edmonton Cmn, Fremont, CA 94555
(510) 505-0744
Related to:
Sriram R Srinivasan, 48Travis Smith, 74Gene A Smith, 70Joyce SmithCharlie Smith, 71
Connected to:
Ananth Iyengar, 67Anirudh S Iyengar, 36Asha D Iyengar, 72Ashvin S Iyengar, 65Kannan N Iyengar, 52Krishnaveni Iyengar, 55Madhu S Iyengar, 50Mrinal A Iyengar, 54Nikishka Iyengar, 35Praveen P Iyengar, 37

Srinivasan Iyengar Phones & Addresses

  • 5375 Edmonton Cmn, Fremont, CA 94555 (510) 505-0744
  • 636 Pinot Blanc Way, Fremont, CA 94539 (510) 284-7839
  • Buffalo, NY
  • Sunnyvale, CA
  • San Jose, CA
  • Santa Clara, CA
  • Alameda, CA

Business Records

Name / Title
Company / Classification
Phones & Addresses
Srinivasan S. Iyengar
President
YAAMAN, INC
Business Services at Non-Commercial Site
6376 Byron Ln, San Ramon, CA 94582

Publications

Us Patents

Analog/Digital Partitioning Of Circuit Designs For Simulation

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US Patent:
7797659, Sep 14, 2010
Filed:
Jan 29, 2007
Appl. No.:
11/699881
Inventors:
Chandrashekar L. Chetput - San Jose CA, US
Abhijeet Kolpekwar - Austin TX, US
Srinivasan Iyengar - Round Rock TX, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 7, 716 1, 716 12, 716 18
Abstract:
For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.

Processor And Method For Writeback Buffer Reuse

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US Patent:
8145848, Mar 27, 2012
Filed:
Nov 30, 2009
Appl. No.:
12/627354
Inventors:
Prashant Jain - San Jose CA, US
Srinivasan R Iyengar - Fremont CA, US
Jeffrey Thomas Oplinger - San Francisco CA, US
Assignee:
Oracle America, Inc. - Redwood City CA
International Classification:
G06F 12/00
US Classification:
711143, 711118, 711128, 711135, 711150, 711156
Abstract:
A processor may include a writeback configured to perform a first writeback operation to store corresponding writeback data back to a lower-level memory upon eviction of the writeback data, and a writeback buffer configured to store the writeback data after the writeback data has been evicted from the writeback cache and before the writeback data has been sent to the lower-level memory. After the writeback data has been sent from the writeback buffer to the lower-level memory, and before the lower-level memory has acknowledged completion of the first writeback operation, the writeback cache may perform a second writeback operation to store different writeback data in the writeback buffer in response to eviction of the different writeback data, such that a total size of the writeback data for the concurrently outstanding writeback operations exceeds a total size of writeback data that the writeback buffer is capable of concurrently storing.

Resource Sharing To Reduce Implementation Costs In A Multicore Processor

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US Patent:
8195883, Jun 5, 2012
Filed:
Jan 27, 2010
Appl. No.:
12/694877
Inventors:
Prashant Jain - San Jose CA, US
Yoganand Chillarige - Sunnyvale CA, US
Sandip Das - Belmont CA, US
Shukur Moulali Pathan - San Jose CA, US
Srinivasan R. Iyengar - Fremont CA, US
Sanjay Patel - San Ramon CA, US
Assignee:
Oracle America, Inc. - Redwood City CA
International Classification:
G06F 13/00
US Classification:
711122, 711118, 711119, 712 32, 712 33, 710100
Abstract:
A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.

Analog/Digital Partitioning Of Circuit Designs For Simulation

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US Patent:
8448116, May 21, 2013
Filed:
Aug 31, 2010
Appl. No.:
12/873162
Inventors:
Chandrashekar L. Chetput - San Jose CA, US
Abhijeet Kolpekwar - Austin TX, US
Srinivasan Iyengar - Round Rock TX, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716119, 716101, 716126
Abstract:
For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.

Resource Sharing To Reduce Implementation Costs In A Multicore Processor

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US Patent:
8516196, Aug 20, 2013
Filed:
Jun 1, 2012
Appl. No.:
13/486091
Inventors:
Prashant Jain - San Jose CA, US
Yoganand Chillarige - Sunnyvale CA, US
Sandip Das - Belmont CA, US
Shukur Moulali Pathan - San Jose CA, US
Srinivasan R. Iyengar - Fremont CA, US
Sanjay Patel - San Ramon CA, US
Assignee:
Oracle America, Inc. - Redwood City CA
International Classification:
G06F 12/00
US Classification:
711122, 711118, 711130, 711131
Abstract:
A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.

Edge-Triggered Scan Flip-Flop And One-Pass Scan Synthesis Methodology

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US Patent:
6389566, May 14, 2002
Filed:
Jun 2, 1998
Appl. No.:
09/088754
Inventors:
Kenneth D. Wagner - Sunnyvale CA
Srinivasan R. Iyengar - Fremont CA
Mehran Amerian - Campbell CA
Assignee:
S3 Incorporated - Santa Clara CA
International Classification:
G01R 3128
US Classification:
714726, 327202
Abstract:
An improved scan flip-flop and method of using same. The scan flip-flop has a separate dedicated scan output driven by a scan output signal driver. Scan shift race conditions are minimized by providing a weak scan output signal driver and inserting delay elements within a cell for a scan flip-flop in the scan signal path. The use of the improved scan flip-flop allows for a one-pass scan synthesis process which provides accurate flip-flop cell timing and area information during the design process.

Multiple Time Domain Network Device Translation

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US Patent:
20220337683, Oct 20, 2022
Filed:
Oct 13, 2021
Appl. No.:
17/500576
Inventors:
- Santa Clara CA, US
Mark BORDOGNA - Andover MA, US
Srinivasan S. IYENGAR - Fremont CA, US
International Classification:
H04L 29/06
Abstract:
Examples described herein relate to a network interface device that includes circuitry to determine a target time domain in which to translate a time stamp associated with a workload and identify the target time domain to cause translation of the time stamp associated with the workload to the target time domain. In some examples, the network interface device stores time domain translation parameters of time stamps from a first time domain to one or more time domains and the network interface device translates the time stamp from the first time domain to the one or more time domains. In some examples, the network interface device comprises circuitry to store time domain translation parameters of time stamps from a first time domain to one or more time domains and the server is to perform translation of the time stamp from the first time domain to the one or more time domains based on the time domain translation parameters.

Method And Apparatus For Data Plane Control Of Network Time Sync Protocol In Multi-Host Systems

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US Patent:
20210211214, Jul 8, 2021
Filed:
Mar 18, 2021
Appl. No.:
17/205869
Inventors:
- Santa Clara CA, US
Srinivasan S. IYENGAR - Fremont CA, US
International Classification:
H04J 3/06
H04L 12/26
H04L 29/06
Abstract:
Methods and apparatus for data plane control of network time sync protocol in multi-host systems. A network interface controller (NIC) is configured to implement a network data plane that is associated with a software-based control plane implemented in the multi-host system. The NIC includes a primary timer and secondary timers at distributed endpoints such as network ports. The NIC receives network time packets having network timestamps and employs a secondary timer to associate a local timestamp with the packets. The network and local timestamps are compared by a network intellectual property block (network IP) in the data plane datapath to adjust the primary and secondary timer(s) to match the network time. The network IP uses a 2-bit wire protocol to increment and/or decrement the primary and secondary timer(s) that enables the timers to be adjusted with a nanosecond granularity.
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Srinivasan R Iyengar from Fremont, CA, age ~59 Get Report