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Anirudh Iyengar Phones & Addresses

  • Hillsboro, OR
  • Centre Hall, PA
  • Tampa, FL

Resumes

Resumes

Anirudh Iyengar Photo 1

Soc Design Engineer At Intel Corporation

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Location:
Hillsboro, OR
Industry:
Research
Work:
Intel Corporation
Soc Design Engineer at Intel Corporation

Penn State University
Graduate Research Assistant

University of South Florida Aug 2014 - May 2016
Graduate Research and Teaching Assistant

University of South Florida Aug 2013 - Aug 2014
Graduate Research Assistant

Athletics Department of Usf Feb 2012 - Jul 2013
Tutor
Education:
Penn State University 2016 - 2018
Doctorates, Doctor of Philosophy, Computer Engineering, Philosophy
University of South Florida 2013 - 2017
Doctorates, Doctor of Philosophy, Computer Engineering, Philosophy
University of South Florida 2011 - 2013
Master of Science, Masters, Electrical Engineering
Manipal Academy of Higher Education 2006 - 2010
Bachelor of Engineering, Bachelors
Sindhi High School
Jain College, No.44/4, District Fund Road, Jayanagar 9Th Block, Bangalore - 69 (2011 - 12)
Sandeepani School of Vlsi Design
University of South Florida
Masters, Master of Science In Electrical Engineering, Computer Engineering, Engineering
Manipal Academy of Higher Education
Skills:
Verilog
Vhdl
System Verilog
Perl
Hspice
Cadence Virtuoso
Fpga
Electronic Circuit Design
Pspice
Xilinx
Labview
Modelsim
Spice
Circuit Design
Xilinx Ise
Digital Signal Processors
Matlab
Microprocessors
Integrated Circuit Design
C
Cadence Spectre
Ni Labview
Simulink
Microsoft Excel
C++
Microsoft Office
Research
Programming
Simulations
Afm
Interests:
Science and Technology
Education
Environment
Languages:
English
Kannada
Hindi
Tamil
Certifications:
Vlsi and Advanced System Design and Verification
Sandeepani School of Vlsi Design
Anirudh Iyengar Photo 2

Anirudh Iyengar

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Publications

Us Patents

Physically Unclonable Function Based On Domain Wall Memory And Method Of Use

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US Patent:
20170062072, Mar 2, 2017
Filed:
Nov 7, 2016
Appl. No.:
15/330829
Inventors:
Swaroop Ghosh - Tampa FL, US
Anirudh Srikant Iyengar - Centre Hall PA, US
Kenneth Ramclam - Tampa FL, US
Assignee:
University of South Florida - Tampa FL
International Classification:
G11C 19/08
Abstract:
A system and method for providing a physically unclonable function (PFU) is described. In operation, the method includes applying a domain wall shift pulse challenge to a plurality of nanowires of a domain wall memory (DWM) array, wherein the nanowires of the domain wall memory (DWM) array have process induced variations, resulting in pinning potentials which affect the velocity of the domain walls along the length of the nanowires. Following the application of the domain wall shift pulse, the response to the challenge is determined by measuring the response of the plurality of nanowires of the domain wall memory to the applied domain wall shift pulse challenge to provide a physically unclonable function (PUF) for the integrated circuit.

Non-Volatile Flip-Flop With Enhanced-Scan Capability To Sustain Sudden Power Failure

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US Patent:
20160322093, Nov 3, 2016
Filed:
May 2, 2016
Appl. No.:
15/144322
Inventors:
Swaroop Ghosh - Tampa FL, US
Anirudh Srikant Iyengar - Tampa FL, US
Jae-Won Jang - Tampa FL, US
Assignee:
University of South Florida - Tampa FL
International Classification:
G11C 11/16
Abstract:
Non-volatile flip-flops (NVFFs) based circuitries and schemes that incorporate magnetic tunnel junctions (MTJs) are provided to ensure fast data storage and restoration from an intentional or unintentional power outage. The NVFFs based circuitries and schemes also include enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The NVFFs based circuitries and schemes eliminate additional write drivers, and may operate at an operation frequency of, for example, up to 2 GHz at a supply voltage of 1.1 V and with 0.55 pJ of energy consumption. A near uniform write latency can be achieved through transistor sizing, given write asymmetry of MTJs. NVFFs based circuitries and schemes incorporating data-dependent power gating circuitries can be used to mitigate high static currents generated during retention and back-to-back writing of identical input data.
Anirudh S Iyengar from Hillsboro, OR, age ~36 Get Report