Songjie Xu Phones & Addresses
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Saratoga, CA
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3161 Sepulveda Blvd, Los Angeles, CA 90034 (310) 391-7850
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3185 Sepulveda Blvd, Los Angeles, CA 90034 (310) 398-2586
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Sunnyvale, CA
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Santa Clara, CA
Publications
Us Patents
Methodology And Applications Of Timing-Driven Logic Resynthesis For Vlsi Circuits
View pageUS Patent:
7219048, May 15, 2007
Filed:
Jan 2, 2001
Appl. No.:
09/754406
Inventors:
Songjie Xu - Los Angeles CA, US
Assignee:
Magma Design Automation, Inc. - San Jose CA
International Classification:
G06F 17/50
G06F 9/455
G06F 9/455
US Classification:
703 19, 716 6
Abstract:
Aspects of the present invention include a methodology for the general timing-driven iterative refinement-based approach, a timing-driven optimization (TDO) method that optimizes the circuit depth after the area oriented logic optimization, and a layout-driven synthesis flow that integrates performance-driven technology mapping and clustering with TDO to account for the effect of mapping and clustering during the timing optimization procedure of TDO. The delay reduction process recursively reduces the delay of critical fanins of a selected. Furthermore, in one embodiment, the fanins of the selected node are sorted according to their slack values.