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Sebastian Turullols

from Los Altos, CA
Age ~50
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Also known as:
Sebastian Turullois, Seabstin Turullols, Turullols Sebastian, Sabastian Turullos
Phone and address:
1868 Robles Ranch Rd, Los Altos, CA 94024
(650) 965-3416
Related to:
Maria L Turullols, 74Roman Turullols, 33Erin M Kan, 52Edwin P Kan, 79Derek L Kan, 43Valerie M Turullols, 41Arvin L Kan, 50Anna M Kan, 79
Connected to:
Sylvia D Turullols, 51Brandon J Turunen, 51Henna P Turunen, 44Jarkko J Turunen, 53Beverly L Turvey, 71Blake R Turvey, 36Carole J Turvey, 87Johnny R Turvey, 65Kayla J Turvey, 36Patricia D Turvey, 79

Sebastian Turullols Phones & Addresses

  • 1868 Robles Ranch Rd, Los Altos Hills, CA 94024 (650) 965-3416 (650) 269-7691
  • 2030 Kent Dr, Los Altos Hills, CA 94024 (650) 965-3416
  • Los Altos, CA
  • Honolulu, HI
  • Santa Rosa, CA
  • Austin, TX
  • Sunnyvale, CA
  • Stanford, CA
  • Cupertino, CA
  • Santa Clara, CA
  • East Peoria, IL
  • Mountain View, CA

Work

Company: Xilinx Nov 2018 Position: Senior director of engineering

Education

Degree: Master of Science, Masters, Bachelors, Bachelor of Science School / High School: Stanford University 1992 to 1999 Specialities: Electrical Engineering

Skills

Hardware • Microprocessors • System Architecture • Rtl Design • Asic • Computer Hardware • Soc • Fpga • Electrical Engineering • Hardware Design

Languages

English

Industries

Computer Hardware

Resumes

Resumes

Sebastian Turullols Photo 1

Senior Director Of Engineering

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Location:
1868 Robles Ranch Rd, Los Altos, CA 94024
Industry:
Computer Hardware
Work:
Xilinx
Senior Director of Engineering
Oracle Feb 2010 - Nov 2018
Senior Director, Hardware Development
Pano Logic Oct 2007 - Jan 2009
Director of Hardware Engineering
Sun Microsystems Oct 2006 - Oct 2007
Hardware Manager
Sun Microsystems 2003 - 2006
Senior Staff Engineer
Education:
Stanford University 1992 - 1999
Master of Science, Masters, Bachelors, Bachelor of Science, Electrical Engineering Austin High School 1988 - 1992
Skills:
Hardware
Microprocessors
System Architecture
Rtl Design
Asic
Computer Hardware
Soc
Fpga
Electrical Engineering
Hardware Design
Languages:
English

Publications

Us Patents

Rapid Datarate Estimation For A Data Stream Multiplexer

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US Patent:
7764717, Jul 27, 2010
Filed:
May 6, 2005
Appl. No.:
11/123820
Inventors:
James J. Yu - San Jose CA, US
Sebastian Turullols - Los Altos CA, US
Aly E. Orady - Sunnyvale CA, US
Assignee:
Oracle America, Inc. - Redwood Shores CA
International Classification:
H04J 3/02
US Classification:
370537, 370271
Abstract:
A multiplexing system having an input unit, a storage unit and control unit. The input unit receives data units corresponding to multiple source data streams and extracts packets from the data units. The control unit computes data rate estimates for the source data streams based on timestamps in the source data streams. The storage unit stores a packet count and previous timestamp value for each source data stream. The control unit computes a preliminary data rate estimate for a source data stream based on samples of a local clock if timestamps are not received promptly. The control unit also computes scheduling rates based on the data rate estimates. The scheduling rates are used to control the rates of allocation of data from the source data streams into a multiplexed output stream. The control unit computes scheduling rates in a way that avoids oversubscription of the output channel.

Conveying Critical Data In A Multiprocessor System

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US Patent:
8261019, Sep 4, 2012
Filed:
Feb 13, 2009
Appl. No.:
12/370757
Inventors:
Sebastian Turullols - Los Altos CA, US
Sumti Jairath - Santa Clara CA, US
Assignee:
Oracle America, Inc. - Redwood City CA
International Classification:
G06F 12/00
G06F 13/00
US Classification:
711118, 711119, 71 35
Abstract:
A system for conveying critical and non-critical words of multiple cache lines includes a first node interface of a first processing node receiving, from a first processor, a first request identifying a critical word of a first cache line and a second request identifying a critical word of a second cache line. The first node interface conveys requests corresponding to the first and second requests to a second node interface of a second processing node. The second node interface receives the corresponding requests and conveys the critical words of the first and second cache lines to the first processing node before conveying non-critical words of the first and second cache lines.

Power-Supply Noise Suppression Using A Frequency-Locked Loop

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US Patent:
8269544, Sep 18, 2012
Filed:
Oct 1, 2010
Appl. No.:
12/896650
Inventors:
David J. Greenhill - Portola Valley CA, US
Robert P. Masleid - Monte Sereno CA, US
Georgios K. Konstadinidis - San Jose CA, US
King C. Yen - San Jose CA, US
Sebastian Turullols - Los Altos CA, US
Assignee:
Oracle America, Inc. - Redwood Shores CA
International Classification:
H03H 11/26
US Classification:
327262, 327291, 327292, 713322
Abstract:
An integrated circuit that includes a digitally controlled oscillator (DCO) that adjusts a clock frequency of a critical path of the integrated circuit based on the variations in a power-supply voltage of the DCO and the critical path is described. This DCO may be included in a feedback control loop that includes a frequency-locked loop (FLL), and which determines an average clock frequency of the critical path based on a reference frequency. Furthermore, the DCO may have a selectable delay characteristic that specifies a delay sensitivity of the DCO as a function of the power-supply voltage, thereby approximately matching a manufactured delay characteristic of the critical path. Additionally, for variations in the power-supply voltage having frequencies greater than a resonance frequency associated with a chip package of the integrated circuit, adjustments of the clock frequency may be proportional to the variations in the power-supply voltage and the selectable delay characteristic.

System And Method For Automatic Communication Lane Failover In A Serial Link

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US Patent:
8332729, Dec 11, 2012
Filed:
Sep 29, 2008
Appl. No.:
12/239960
Inventors:
Ramaswamy Sivaramakrishnan - San Jose CA, US
Sebastian Turullols - Los Altos CA, US
Stephen E. Phillips - Los Gatos CA, US
Assignee:
Oracle International Corporation - Redwood City CA
International Classification:
H03M 13/00
US Classification:
714776, 714710, 714718, 711154, 365 63
Abstract:
A system for automatic lane failover includes a first device coupled to a second device via a serial communication link having a plurality of a communication lanes. The devices may communicate by operating the link in a normal mode and a degraded mode. During normal mode operation, the devices may send frames of information to each other via the serial communication link. Each frame of information may include a number of data bits and a number of error protection bits. In response to either device detecting a failure of one or more of the communication lanes, the first device may cause the serial communication link to operate in a degraded mode by removing the one or more failed communication lanes. In addition, each device may reformat and send the frame of information on the remaining communication lanes with fewer data bits and the same number of error protection bits.

Noise Suppression Using An Asymmetric Frequency-Locked Loop

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US Patent:
8604852, Dec 10, 2013
Filed:
Sep 11, 2012
Appl. No.:
13/610469
Inventors:
Sebastian Turullols - Los Altos CA, US
Changku Hwang - Morgan Hill CA, US
Daniel Woo - San Francisco CA, US
Assignee:
Oracle International Corporation - Redwood Shores CA
International Classification:
H03L 7/06
US Classification:
327159, 327298, 327262
Abstract:
In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency that is less than the first fundamental frequency. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage so that an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced. For example, the control logic may select the first DCO if the instantaneous value of the power-supply voltage is greater than the average power-supply voltage; otherwise, the control logic may select the second DCO.

Voltage Calibration Method And Apparatus

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US Patent:
20120218034, Aug 30, 2012
Filed:
Feb 28, 2011
Appl. No.:
13/036285
Inventors:
Sebastian Turullols - Los Altos CA, US
Ali Vahidsafa - Palo Alto CA, US
David Greenhill - , US
International Classification:
G05F 1/10
US Classification:
327540
Abstract:
A method and apparatus for power supply calibration to reduce voltage guardbands is disclosed. In one embodiment, an integrated circuit (IC) includes a voltage measurement unit configured to measure an operating voltage during a start-up procedure. The IC further includes a comparator configured to compare the measured operating voltage to a target voltage. The comparator is further configured to cause a change to a supply voltage (upon which the operating voltage is based) if the operating voltage is not within a target voltage range and to repeat the measurement of the operating voltage. If the operating voltage is within the target voltage range, the comparator is configured to inhibit further changes to the operating voltage.

Constant Frequency Architectural Timer In A Dynamic Clock Domain

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US Patent:
20130311814, Nov 21, 2013
Filed:
May 15, 2012
Appl. No.:
13/472105
Inventors:
Sebastian Turullols - Los Altos CA, US
Ali Vahidsafa - Palo Alto CA, US
Assignee:
Oracle International Corporation - Redwood City CA
International Classification:
G06F 1/04
G06F 1/12
US Classification:
713401, 713500, 713400
Abstract:
Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system.

Coherent Data Forwarding When Link Congestion Occurs In A Multi-Node Coherent System

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US Patent:
20140040526, Feb 6, 2014
Filed:
Jul 31, 2012
Appl. No.:
13/563586
Inventors:
Bruce J. Chang - Saratoga CA, US
Sebastian Turullols - Los Altos CA, US
Brian F. Keish - San Jose CA, US
Damien Walker - San Jose CA, US
Ramaswamy Sivaramakrishnan - San Jose CA, US
Paul N. Loewenstein - Palo Alto CA, US
International Classification:
G06F 13/38
US Classification:
710316
Abstract:
Systems and methods for efficient data transport across multiple processors when link utilization is congested. In a multi-node system, each of the nodes measures a congestion level for each of the one or more links connected to it. A source node indicates when each of one or more links to a destination node is congested or each non-congested link is unable to send a particular packet type. In response, the source node sets an indication that it is a candidate for seeking a data forwarding path to send a packet of the particular packet type to the destination node. The source node uses measured congestion levels received from other nodes to search for one or more intermediate nodes. An intermediate node in a data forwarding path has non-congested links for data transport. The source node reroutes data to the destination node through the data forwarding path.
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Sebastian Turullols from Los Altos, CA, age ~50 Get Report