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Qidao Li

from Boise, ID
Age ~41
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Also known as:
Li Qidao
Phone and address:
11328 W Napia St, Boise, ID 83709
Related to:
Mandi Yu, 48Mingming Yu, 55Yuan D LiXiao Lin Yu, 74Elliott Aili, 50Jose J Guzman, 48Qiwei Li, 45Donna M Kilpatrick, 67Zhengbiao O Li, 72Josha GuzmanLuciano Guzman, 44Remedios GuzmanAlvaro V Guzman, 42Wen Chu, 75Youbiao Li, 70Jianbiao Li, 78Kunyu Yi, 49Feinan Li, 75Xiaolin Lin Yu
Connected to:
Ai Q Li, 64Ai H Li, 81Aida Li, 67Aijun Li, 65Aiwen Q Li, 56Aiyan Li, 61Alan Li, 80Alice Li, 46Alida Li, 59Alisha Li, 31

Qidao Li Phones & Addresses

  • 11328 W Napia St, Boise, ID 83709
  • Colorado Springs, CO
  • 107 W Arvada St APT 8, Colorado Spgs, CO 80905 (719) 520-5107

Work

Company: Cypress semiconductor corporation Nov 2012 to Aug 2015 Position: Design engineer

Education

Degree: Master of Science, Bachelors, Masters, Master of Science In Electrical Engineering, Bachelor of Science School / High School: University of Colorado Colorado Springs 2003 to 2007 Specialities: Electrical Engineering

Skills

Ic • Mixed Signal • Asic • Cmos • Integrated Circuit Design • Verilog • Timing Closure • Primetime • Rtl Design • Static Timing Analysis • Semiconductors • Soc • Rtl Coding • Visual C# • Fpga Prototyping • Firmware • Visual C++ • Perl Script • Synthesis • System Verilog • Systemverilog • Logic Synthesis • Simulations • Low Power Design • Embedded Systems • Fpga • Analog Circuit Design • Xilinx • Test Engineering • Vhdl • Spice • Microcontrollers • Field Programmable Gate Arrays • Integrated Circuits • Perl • Functional Verification • Application Specific Integrated Circuits

Languages

Mandarin

Interests

Science and Technology • Education • Economic Empowerment

Industries

Semiconductors

Resumes

Resumes

Qidao Li Photo 1

Design Verification Engineer

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Location:
Boise, ID
Industry:
Semiconductors
Work:
Cypress Semiconductor Corporation Nov 2012 - Aug 2015
Design Engineer
Micron Technology Nov 2012 - Aug 2015
Design Verification Engineer
Ramtron International Corporation Jan 2008 - Nov 2012
Ferro Memory Design Engineer
Ramtron Jan 2008 - Nov 2012
Design Engineer
Vision & Security Laboratory Apr 2006 - Dec 2007
Research Assistant
Education:
University of Colorado Colorado Springs 2003 - 2007
Master of Science, Bachelors, Masters, Master of Science In Electrical Engineering, Bachelor of Science, Electrical Engineering Palmer High School
Skills:
Ic
Mixed Signal
Asic
Cmos
Integrated Circuit Design
Verilog
Timing Closure
Primetime
Rtl Design
Static Timing Analysis
Semiconductors
Soc
Rtl Coding
Visual C#
Fpga Prototyping
Firmware
Visual C++
Perl Script
Synthesis
System Verilog
Systemverilog
Logic Synthesis
Simulations
Low Power Design
Embedded Systems
Fpga
Analog Circuit Design
Xilinx
Test Engineering
Vhdl
Spice
Microcontrollers
Field Programmable Gate Arrays
Integrated Circuits
Perl
Functional Verification
Application Specific Integrated Circuits
Interests:
Science and Technology
Education
Economic Empowerment
Languages:
Mandarin

Publications

Us Patents

Authenticating Ferroelectric Random Access Memory (F-Ram) Device And Method

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US Patent:
20120204040, Aug 9, 2012
Filed:
Jan 20, 2012
Appl. No.:
13/355145
Inventors:
Kurt S. Schwartz - Colorado Springs CO, US
Qidao Li - Colorado Springs CO, US
Michael Borza - Ottawa, CA
Assignee:
Ramtron International Corporation - Colorado Springs CO
International Classification:
G06F 21/04
G06F 12/14
US Classification:
713193, 726 2
Abstract:
An F-RAM authenticating memory device and method providing secure mutual authentication between a Host system and a memory in order to gain read/write access to the F-RAM user memory contents. The device and technique of the present invention uses an Advanced Encryption Standard AES128 encryption module in conjunction with a true hardware random number generator and basic exclusive OR (XOR) functions in order to achieve a secure algorithm with a relatively small amount of processing. Due to inherently faster write times than that of conventional floating gate non-volatile memory technologies, the use of F-RAM significantly reduces the time available to interfere with a critical security parameter (CSP) update. Moreover, unlike floating gate technologies, F-RAM's read vs. write current signature is balanced making it less prone to side channel attacks while also providing relatively faster erase times.

Non-Volatile Static Ram And Method Of Operation Thereof

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US Patent:
20160365145, Dec 15, 2016
Filed:
Sep 24, 2015
Appl. No.:
14/864594
Inventors:
- San Jose CA, US
Donald J. VERHAEGHE - Colorado Springs CO, US
Alan DeVilbiss - Colorado Springs CO, US
Qidao Li - Colorado Springs CO, US
Fan CHU - Colorado Springs CO, US
Judith Allen - Monument CO, US
International Classification:
G11C 14/00
G11C 11/419
G11C 11/22
Abstract:
A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM) circuit, in which the F-RAM circuit stores a bit of data from the SRAM circuit during power-out periods, the F-RAM circuit is further coupled to bit-line(s) to output the bit of data stored in the F-RAM circuit when operation power is restored.
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Qidao Li from Boise, ID, age ~41 Get Report