Ngo Thanh Ho

6438429, Aug 20, 2002

Dec 3, 1999

09/454796

Tan Thanh Ho - Santa Clara CA
Scott William Mitchell - San Jose CA
Andrew Nakao - Fremont CA
Ngo Thanh Ho - San Jose CA
George Kwan - Sunnyvale CA

3Com Corporation - Santa Clara CA

G06F 126

700 22, 713340

A circuit and method thereof for indicating availability of a power source other than a first power source in a computer system peripheral device (such as a network adapter) connected to a plurality of power sources including. The circuit includes a circuit subassembly coupled to the first power source and a second power source. The circuit subassembly conducts current from the first power source when power is not available from the second power source and otherwise conducts current from the second power source. A first component is coupled to the circuit subassembly and conducts current when the second power source is available; otherwise, it does not conduct current. A second component is coupled to the circuit subassembly and to the first component. The second component conducts current when the first component is conducting current and otherwise does not conduct current. An output lead is coupled to the second component, and the output lead provides a signal indicating the second power source is available.

6556580, Apr 29, 2003

Dec 16, 1999

09/465984

Ngo Thanh Ho - San Jose CA
Krishna Uppunda - Santa Clara CA

3Com Corporation - Santa Clara CA

H04L 1256

370412, 370462, 713 2, 709250

A transmit packet buffer (TPB) is used on a network interface card (NIC) to store downloaded packets and forward them through the media access controller (MAC) and the physical layer interface (PHY) onto the wire. A multi-function TPB is implemented to allow the multiple usage of this buffer. Packets may be downloaded to this buffer through multiple sources. Different types of the packets may each be stored at predefined locations. For example, while the second half of the TPB is used to transmit keep-alive or alert-on-LAN packets, the first half may be used to compare received packets with a wake-up pattern for system wake-up. With multi-function support, various PC management functions may be implemented more effectively and with reduced cost.

6560714, May 6, 2003

Dec 3, 1999

09/454676

Tan Thanh Ho - Santa Clara CA
Scott William Mitchell - San Jose CA
Andrew Nakao - Fremont CA
Ngo Thanh Ho - San Jose CA
George Kwan - Sunnyvale CA

3Com Corporation - Santa Clara CA

G06F 126

713340, 713310

A circuit and method thereof for arbitrating between a plurality of power sources connected to a computer system peripheral device. The circuit includes a first circuit subassembly coupled to a first power source and a second power source. The first circuit subassembly conducts current from the first power source when power is not available from the second power source, and otherwise conducts current from the second power source. The circuit also includes a second circuit subassembly coupled between the first circuit subassembly and a third power source. The second circuit subassembly conducts current from the third power source when the third power source is available and otherwise conducts current from the first circuit subassembly. The second circuit subassembly comprises a first component, a second component and a third component. The first component is coupled to the third power source and the first circuit subassembly.

6564333, May 13, 2003

Dec 3, 1999

09/454468

Tan Thanh Ho - Santa Clara CA
Scott William Mitchell - San Jose CA
Ryan Hirth - Windsor CA
Ngo Thanh Ho - San Jose CA

3Com Corporation - Santa Clara CA

G06F 126

713340, 713310

A circuit and method thereof for arbitrating between a first power source and a second power source in a computer system peripheral device such as a network adapter (e. g. , a network interface card) that is connected to multiple power sources. The circuit includes a field effect transistor (FET) and a diode integral with the FET coupled between the first power source and the second power source. The FET is adapted to conduct current from the second power source when power is not available from the first power source, and to substantially prevent current from flowing from the first power source to the second power source. The circuit also includes a voltage regulator coupled between the first power source and the second power source, adapted to regulate voltage such that a voltage from the first power source and a voltage from the second power source are approximately equal.

6760781, Jul 6, 2004

Feb 16, 2000

09/505069

Ngo Thanh Ho - San Jose CA

3Com Corporation - Santa Clara CA

G06F 1516

709250, 709226, 709235, 709237, 709243, 710 53, 714748, 713322, 370216, 370336

Autonomous retransmission of data packets onto a network from a Network Interface Card level upon command from a host processor is support. Efficient FIFO buffering in an ASIC is retained. Uses for autonomous retransmission include hardware and software testing and in network management. One unique process includes: (a) downloading at least one data packet from the host processor to a buffer; (b) storing a parameter indicating a number of retransmissions; (c) transferring packets from the buffer toward the network until all packets of the at least one data packet have been transferred towards the network; and (d) checking a parameter stored on the network interface apparatus, and in response to a particular value of the stored parameter indicating no retransmission, ending the transferring, and in response to other values of the stored parameter, repeating transferring of a last packet in the buffer until the number of retransmissions has been executed or until the host processor commands a cessation of the transferring.

7349537, Mar 25, 2008

Mar 10, 2005

11/078923

Glen Kramer - Petaluma CA, US
Lawrence D. Davis - Petaluma CA, US
Edward W. Boyd - Petaluma CA, US
Ryan E. Hirth - Windsor CA, US
Ngo Thahn Ho - Arlington TX, US

Teknovus, Inc. - Petaluma CA

H04K 1/00
H04L 9/00
H04L 9/28
H04J 14/00

380 28, 380256, 380277, 380284, 398 71, 713160

One embodiment of the present invention provides a system that decrypts downstream data in an Ethernet passive optical network (EPON). During operation, the system receives a data frame which is encrypted based on a remote input block and a session key, wherein the remote input block is constructed based on a remote cipher counter and a remote block counter. The system adjusts a local cipher counter based on a received checksum located in a preamble of the data frame, wherein the local cipher counter is substantially synchronized with the remote cipher counter. In addition, the system truncates the local cipher counter by discarding n least significant bits thereof. The system then constructs a local input block based on the truncated cipher counter and a local block counter for the received data frame. Next, the system decrypts the data frame based on the local input block and the session key.

8335316, Dec 18, 2012

Mar 31, 2009

12/414963

Ryan E Hirth - Windsor CA, US
Edward W Boyd - Petaluma CA, US
Ngo Thanh Ho - Arlington TX, US

Broadcom Corporation - Irvine CA

H04K 1/00

380256

One embodiment provides a system for decrypting data frames in an Ethernet passive optical network (EPON). During operation, the system maintains a local cipher counter at a local node, and receives from a remote node a data frame which is encrypted based on a remote input block and a session key. The remote input block is constructed based on the remote cipher counter and a remote block counter. The system updates the local cipher counter based on a received field located in a preamble of the data frame, truncates the local cipher counter by discarding a number of least significant bits, and constructs for the received data frame a local input block based on the truncated local cipher counter, the received field, and a local block counter. The system then decrypts the data frame based on the local input block and the session key.

6324652, Nov 27, 2001

Jan 15, 1999

9/232862

Nathaniel Henderson - San Jose CA
David Brown - San Jose CA
Ngo Ho - San Jose CA

3COM Corporation - Santa Clara CA

G06F 104

713500

An asynchronous switching circuit for multiple indeterminate bursting clocks. In one embodiment, the present invention recites a clock-switching circuit that provides a single unclipped and glitch-free clock signal at its output from among multiple clock inputs. The clock-switching circuit is comprised of a plurality of asynchronously-enabled clock circuits, a plurality of blocking circuits, a synchronizing clock, and a logic gate. Each of the plurality of blocking circuits has an input lead respectively coupled to one of the plurality of asynchronously-enabled clock circuits, each of the plurality of blocking circuits also has an output coupled to all of the plurality of asynchronously-enabled clock circuits except the one to which its input is coupled. The synchronizing clock is coupled to each of the plurality of blocking circuits while the logic gate is coupled to each of the plurality of asynchronously-enabled clock circuits.