Monty M Denneau

6384833, May 7, 2002

Aug 10, 1999

09/371395

Monty Montague Denneau - Brewster NY
Peter Heiner Hochschild - New York NY

International Business Machines Corporation - Armonk NY

G06T 1500

345522, 345502, 345505, 345506

The geometric processing of an ordered sequence of graphics commands is distributed over a set of processors by the following steps. The sequence of graphics commands is partitioned into an ordered set of N subsequences S. . . S , and an ordered set of N state vectors V. . . V is associated with said ordered set of subsequences S. . . S. A first phase of processing is performed on the set of processors whereby, for each given subsequence S in the set of subsequences S. . . S , state vector V is updated to represent state as if the graphics commands in subsequence S had been executed in sequential order. A second phase of the processing is performed whereby the components of each given state vector V in the set of state vectors V. . . V generated in the first phase is merged with corresponding components in the preceding state vectors V. . . V such that the state vector V represents state as if the graphics commands in subsequences S. . .

6836015, Dec 28, 2004

May 2, 2003

10/428960

Monty M. Denneau - Brewster NY
Dinesh Gupta - Hopewell Junction NY
Lisa J. Jimarez - Chandler AZ
Steven Ostrander - Poughkeepsie NY
Brenda L. Peterson - Wappingers Falls NY
Mark V. Pierson - Binghamton NY
Eugen Schenfeld - Mounmouth Junction NJ
Subhash L. Shinde - Cortlandt Manor NY

International Business Machines Corporation - Armonk NY

H01L 2334

257706, 257684

Optical cubes and optical cube assemblies for directing optical beams are provided. The optical cubes are optically transparent modules that can be adapted to reflect, transmit, and/or partially reflect and transmit optical beams. The optical cubes may include bi-direction or multi-direction beam directing elements for directing optical beams. The optical cube assemblies may include flexible chip assemblies attached to optical cubes. The chip assemblies may include vertical cavity surface-emitting lasers for emitting optical beams or receivers for receiving optical beams mounted on a flexible and electrical interconnect mounting assembly.

6961782, Nov 1, 2005

Mar 14, 2000

09/525707

Monty M. Denneau - Brewster NY, US
Peter H. Hochschild - New York NY, US
Richard A. Swetz - Mahopac NY, US

International Business Machines Corporation - Armonk NY

G06F015/173

709241, 370351, 370380, 370400, 712 11

There is provided a method for routing packets on a linear array of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves. The method may optionally include the step of randomly sending the packet using either of the sending steps, when the result is equal to N/2 moves and N is an even number.

6961804, Nov 1, 2005

Jun 28, 2002

10/186476

Monty Montague Denneau - Brewster NY, US
Peter Heiner Hochschild - New York NY, US

International Business Machines Corporation - Armonk NY

G06F012/00

711 3, 711119, 711130, 711148, 711202

Caches are associated with processors, such multiple caches may be associated with multiple processors. This association may be different for different main memory address ranges. The techniques of the invention are flexible, as a system designer can choose how the caches are associated with processors and main memory banks, and the association between caches, processors, and main memory banks may be changed while the multiprocessor system is operating. Cache coherence may or may not be maintained. An effective address in an illustrative embodiment comprises an interest group and an associated address. The interest group is an index into a cache vector table and an entry into the cache vector table and the associated address is used to select one of the caches. This selection can be pseudo-random. Alternatively, in some applications, the cache vector table may be eliminated, with the interest group directly encoding the subset of caches to use.

7072970, Jul 4, 2006

Oct 5, 2001

09/682688

Christos J. Georgiou - Scarsdale NY, US
Monty M. Denneau - Brewster NY, US
Valentina Salapura - Yorktown Heights NY, US
Robert M. Bunce - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

G06F 15/16
H04L 12/28
H04L 3/22

709230, 709238, 370389, 370401, 370466

An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via high-speed interconnect, and each processor's memory is globally accessible by other processors. Each processor has multiple threads, each capable of fully executing programs. Each processors contains embedded dynamic random access memory (DRAM). Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify relates frames. Related frames are dispatch to the same thread so as to minimize the overhead associated with memory accesses and general protocol processing. The high-speed protocol handler may also provide built-in monitors for examining the activity of its hardware resources and reallocating the workload to the resources that are not heavily used, thus balancing the resource utilization and increasing the workload throughput.

7203790, Apr 10, 2007

Aug 5, 2005

11/197899

Monty Montague Denneau - Brewster NY, US
Peter Heiner Hochschild - New York NY, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711 3, 711119, 711130, 711148, 711202

Caches are associated with processors, such multiple caches may be associated with multiple processors. This association may be different for different main memory address ranges. The techniques of the invention are flexible, as a system designer can choose how the caches are associated with processors and main memory banks, and the association between caches, processors, and main memory banks may be changed while the multiprocessor system is operating. Cache coherence may or may not be maintained. An effective address in an illustrative embodiment comprises an interest group and an associated address. The interest group is an index into a cache vector table and an entry into the cache vector table and the associated address is used to select one of the caches. This selection can be pseudo-random. Alternatively, in some applications, the cache vector table may be eliminated, with the interest group directly encoding the subset of caches to use.

7477608, Jan 13, 2009

Jul 21, 2005

11/186693

Monty M. Denneau - Brewster NY, US
Peter H. Hochschild - New York NY, US
Richard A. Swetz - Mahopac NY, US

International Business Machines Corporation - Armonk NY

H04L 12/26
H04L 12/66
G06F 15/00

370241, 370353, 370380, 370400, 712 11

There is provided a method for routing packets on a linear of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves. The method may optionally include the step of randomly sending the packet using either of the sending steps, when the result is equal to N/2 moves and N is an even number.

7676588, Mar 9, 2010

Mar 24, 2006

11/387875

Christos John Georgiou - Scarsdale NY, US
Monty Montague Denneau - Brewster NY, US

International Business Machines Corporation - Armonk NY

G06F 15/16
G06F 3/00

709230, 709201, 709232, 710 1, 710 52

An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via a high-speed interconnect, using a multi-token counter protocol for data transmission between processors and between processors and memory. Each processor's memory is globally accessible by other processors, and memory synchronization operations are used to obviate the need for “spin-locks”. Each processor has multiple threads, each capable of fully executing programs. Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify related frames. Related frames are dispatched to the same thread so as to minimize the overhead associated with memory accesses and general protocol processing.