Maria Alicia Chan

6352930, Mar 5, 2002

Mar 22, 2001

09/814636

Kathleen R. Early - Santa Clara CA
Suzette K. Pangrle - Cupertino CA
Maria C. Chan - San Jose CA
Lewis Shen - Cupertino CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21302

438694, 428698, 438584, 438585, 438 72, 438717, 438736

In the manufacture of sub-0. 35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.

6448594, Sep 10, 2002

Mar 30, 2000

09/539307

Maria C. Chan - San Jose CA
Hao Fang - Cupertino CA
Lu You - Santa Clara CA
Mark S. Chang - Los Altos CA
King Wai Kelwin Ko - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2976

257288, 257368, 257412, 257413, 257900

In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the oxide spacers is triangular shaped. In a second aspect of the present invention, a method and system for processing a semiconductor device is disclosed. The method and system for processing a semiconductor comprise forming at least two gate stacks over a semiconductor substrate, depositing an oxide layer over the at least two gate stacks, and etching the oxide layer to form at least one oxide spacer in between the at least two gate stacks, wherein the at least one oxide spacer is triangular shape. Through the use the present invention, the voids that are created in the semiconductor device during conventional semiconductor processing are eliminated. This is accomplished by creating oxide spacers having a triangular shape when etching the oxide layer to form the oxide spacer.

6455888, Sep 24, 2002

Feb 17, 2000

09/506298

Kathleen R. Early - Santa Clara CA
Michael K. Templeton - Atherton CA
Nicholas H. Tripsas - San Jose CA
Maria C. Chan - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 29788

257315, 438701

A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.

6495435, Dec 17, 2002

Feb 15, 2001

09/788246

Michael K. Templeton - Atherton CA
Hao Fang - Cupertino CA
Maria C. Chan - San Jose CA

Advance Micro Devices, Inc. - Sunnyvale CA

H01L 2120

438584, 430325

A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask. The method and system also preferably include removing a second portion of the layer of material exposed by the pattern of the physical mask to form the plurality of lines.

6593245, Jul 15, 2003

Aug 1, 1996

08/690848

Maria Chan - San Jose CA

Advanced Micro Devices - Sunnyvale CA

B44C 122

438724, 438744

A method for plasma etching of silicon nitride using a mixture of trifluoromethane and oxygen in a ratio of approximately 8 to 1 to selectively etch silicon nitride in preference to silicon dioxide and photoresist, resulting in critical dimension gain.

6603211, Aug 5, 2003

Feb 15, 2001

09/784907

Michael K. Templeton - Atherton CA
Hao Fang - Cupertino CA
Maria C. Chan - San Jose CA
King Wai Kelwin Ko - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 23544

257797

A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.

6610580, Aug 26, 2003

May 2, 2000

09/563179

Maria C. Chan - San Jose CA
Hao Fang - Cupertino CA
Mark S. Chang - Los Altos CA
Mike Templeton - Atherton CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2176

438424, 438435, 438439, 438443, 438444

In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced. In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back.

7012008, Mar 14, 2006

Dec 1, 2000

09/728554

Jeffrey A. Shields - Sunnyvale CA, US
Tuan D. Pham - San Jose CA, US
Mark T. Ramsbey - Sunnyvale CA, US
Yu Sun - Saratogo CA, US
Angela T. Hui - Fremont CA, US
Maria Chow Chan - San Jose CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21/31

438305, 438258, 438275, 438303, 438537, 438595

In a two-step spacer fabrication process for a non-volatile memory device, a thin oxide layer is deposited on a wafer substrate leaving a gap in the core of the non-volatile memory device. Implantation and/or oxide-nitride-oxide removal can be accomplished through this gap. After implantation, a second spacer is deposited. After the second spacer deposition, a periphery spacer etch is performed. By the above method, a spacer is formed.