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Lordson L Yue

from Los Altos, CA
Age ~61
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Also known as:
Lordson Lawrence Yue, Lawrence Yue Lordson, Yue Lordson
Phone and address:
1832 Grant Park Ln, Los Altos, CA 94024
(650) 867-0505
Related to:
Linda Y Yue, 88Carrie Chen, 81Cynthia C Yue, 64Robert Karmein Yue, 64Stanley L Yue, 99Carrie Chen, 64Wei ChenWei T Chen, 81Sun Y Yue, 87Sai Mei Chen
Connected to:
Allan W Yue, 38Ann S Yue, 84Bingfang Yue, 56Changbiao Yue, 75Cheisan Yue, 71Darren Yue, 37Fan T Yue, 59Gene M Yue, 67Guosen Yue, 52Hai Yue, 43

Lordson Yue Phones & Addresses

  • 1832 Grant Park Ln, Los Altos, CA 94024 (650) 867-0505
  • 313 Thatcher Ln, San Mateo, CA 94404
  • Foster City, CA
  • Sunnyvale, CA
  • Woodside, CA
  • San Francisco, CA
  • Mountain View, CA

Work

Company: Nvidia Oct 2002 to Oct 2019 Position: Principal engineer

Education

Degree: Master of Science, Masters School / High School: University of California, Berkeley Specialities: Electrical Engineering, Electrical Engineering and Computer Science, Computer Science

Skills

Asic • Soc • Rtl Design • Computer Architecture • Processors • Debugging • Microprocessors • Vlsi • Static Timing Analysis • Systemverilog • Hardware Architecture • Eda • Fpga • High Performance Computing • Algorithms

Languages

English

Industries

Computer Hardware

Resumes

Resumes

Lordson Yue Photo 1

Senior Asic Manager

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Location:
1832 Grant Park Ln, Los Altos, CA 94024
Industry:
Computer Hardware
Work:
Nvidia Oct 2002 - Oct 2019
Principal Engineer
Nvidia Oct 2002 - Oct 2019
Senior Asic Manager
Terablaze Jan 2002 - Oct 2002
Project Lead
Pmc-Sierra Jan 1998 - Jan 2001
Design Lead
Amd Jan 1995 - Jan 1998
Senior Hardware Engineer
Education:
University of California, Berkeley
Master of Science, Masters, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science University of California, Berkeley
Bachelors, Bachelor of Science, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science
Skills:
Asic
Soc
Rtl Design
Computer Architecture
Processors
Debugging
Microprocessors
Vlsi
Static Timing Analysis
Systemverilog
Hardware Architecture
Eda
Fpga
High Performance Computing
Algorithms
Languages:
English

Publications

Us Patents

Circuit And Method For Detecting Bank Conflicts In Accessing Adjacent Banks

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US Patent:
6393512, May 21, 2002
Filed:
Sep 27, 1999
Appl. No.:
09/407224
Inventors:
Andrea Y. J. Chen - Sunnyvale CA
Lordson L. Yue - Foster City CA
Assignee:
ATI International SRL
International Classification:
G06F 1200
US Classification:
711 5
Abstract:
A bank conflict detector compares at least a portion of a current address signal (i. e. an address signal generated by a request currently issued to main memory) with a corresponding portion of a to-be-issued memory address signal, to determine if a bank conflict exists. Specifically, in one embodiment, the bank conflict detector includes a number of exclusive OR gates that receive as inputs the two addresses to be compared, and generate an output (also called âXOR resultâ) that is compared with predetermined patterns to determine if a bank conflict exists. For example, if the bank conflict detector finds that the XOR result is 0 (zero) then the two addresses access the same bank. The bank conflict detector also the XOR result with patterns that are formed by a number of consecutive 1 in the least significant bits and a number of consecutive 0 in the most significant bits. If no match, then the bank conflict detector determines that no bank conflict exists.

Scheduler For Avoiding Bank Conflicts In Issuing Concurrent Requests To Main Memory

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US Patent:
6393534, May 21, 2002
Filed:
Sep 27, 1999
Appl. No.:
09/407131
Inventors:
Andrea Y. J. Chen - Sunnyvale CA
Lordson L. Yue - Foster City CA
Assignee:
ATI International SRL - Barbados
International Classification:
G06F 1200
US Classification:
711158, 711 5
Abstract:
A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler issues requests from the store to the main memory in an order different from the order in which the requests are received, for example, to avoid bank conflicts. In this example, the main memory scheduler issues a first request to a first memory bank that is not coincident with (and in case of dependent banks, not adjacent to) a second memory bank (that is being currently accessed) prior to issuing a second request to a memory bank that is coincident with the (or adjacent to) second memory bank. Moreover, the main memory scheduler issues a refresh request prior to issuing a read request or a write request even if the refresh request was most recently received, thereby to prioritize the refresh request ahead of read and write requests. Similarly, the main memory scheduler prioritizes a majority of read requests ahead of write requests, so that a processor that originates a read request is not normally stalled by a previously issued write request, as would be the case in first-in-first-out (FIFO) issuance of memory requests. The main memory scheduler performs FIFO processing, for example, when a later-received read request and an earlier-received write request both access the same location in main memory, or when the number of pending write requests exceeds a predetermined limit.

Scheduler For Avoiding Bank Conflicts In Issuing Concurrent Requests To Main Memory

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US Patent:
6507886, Jan 14, 2003
Filed:
May 1, 2001
Appl. No.:
09/847914
Inventors:
Andrea Y. J. Chen - Sunnyvale CA
Lordson L. Yue - Foster City CA
Assignee:
ATI International SRL - Barbados
International Classification:
G06F 1200
US Classification:
711 5, 711156, 711158, 711159, 710 52, 710310
Abstract:
A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler issues requests from the store to the main memory in an order different from the order in which the requests are received, for example, to avoid bank conflicts. In this example, the main memory scheduler issues a first request to a first memory bank that is not coincident with (and in case of dependent banks, not adjacent to) a second memory bank (that is being currently accessed) prior to issuing a second request to a memory bank that is coincident with the (or adjacent to) second memory bank. Moreover, the main memory scheduler issues a refresh request prior to issuing a read request or a write request even if the refresh request was most recently received, thereby to prioritize the refresh request ahead of read and write requests. Similarly, the main memory scheduler prioritizes a majority of read requests ahead of write requests, so that a processor that originates a read request is not normally stalled by a previously issued write request, as would be the case in first-in-first-out (FIFO) issuance of memory requests. The main memory scheduler performs FIFO processing, for example, when a later-received read request and an earlier-received write request both access the same location in main memory, or when the number of pending write requests exceeds a predetermined limit.

Approximation Circuit And Method

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US Patent:
6581085, Jun 17, 2003
Filed:
May 12, 1999
Appl. No.:
09/310184
Inventors:
Lordson L. Yue - Foster City CA
Parin B. Dalal - Milpitas CA
Avery Wang - Redwood City CA
Assignee:
ATI International SrL - Christchurch
International Classification:
G06F 738
US Classification:
708502
Abstract:
An approximation circuit approximates a function f(x) of an input value âxâ by adding at least the first two terms in a Taylor series (i. e. , f(a) and fâ(a)(x-a)) where âaâ is a number reasonably close to value âxâ. The first term is generated by a first look-up table which receives the approximation value âaâ. The first look-up table generates a function f(a) of the approximation value âaâ. The second look-up table generates a first derivative fâ(a) of the function f(a). A first multiplier then multiplies the first derivative fâ(a) by a difference (x-a) between input value âxâ and approximation value âaâ to generate a product fâ(a)(x-a). The approximation circuit can approximate the function f(x) by adding the third term of the Taylor series, (Â)fâ(a)(x-a).

Optimal Initial Rasterization Starting Point

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US Patent:
7224364, May 29, 2007
Filed:
Feb 3, 1999
Appl. No.:
09/244270
Inventors:
Lordson L. Yue - Foster City CA, US
James T. Battle - San Jose CA, US
Assignee:
ATI International SRL - Christchurch
International Classification:
G06T 11/00
G06T 11/20
US Classification:
345468, 345441
Abstract:
A frame buffer is divided into tiles of, for example, 32 by 32 pixels. Triangles (and portions thereof) that are within a given tile are rasterized one triangle at a time into the tile location. This process repeats for each tile in the image frame. A sorting circuit generates control bits representing a vertical order of the vertices of a current triangle. A series of multiplexers vertically sorts the vertices bases on these control bits. A region calculation circuit generates region bits representing a location each of the vertices with respect to the current tile. A trivial discard of the triangle data occurs if the region bits indicate that the entire triangle lies outside of the tile. Subsequently, an initial rasterization starting point is estimated based on the region bits to lower the time needed for the rasterizer to find the first pixel of the current triangle to be assigned values.

Apparatus, System, And Method For Clipping Graphics Primitives With Reduced Sensitivity To Vertex Ordering

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US Patent:
7292254, Nov 6, 2007
Filed:
Dec 5, 2005
Appl. No.:
11/294791
Inventors:
Lordson L. Yue - Foster City CA, US
Vimal S. Parikh - Fremont CA, US
Andrew J. Tao - San Francisco CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G09G 5/00
G06T 1/00
US Classification:
345620, 345619, 345418
Abstract:
Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation. The clipping engine is configured to perform a set of clipping operations with respect to the canonical representation.

Apparatus, System, And Method For Clipping Graphics Primitives With Accelerated Context Switching

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US Patent:
7420572, Sep 2, 2008
Filed:
Dec 19, 2005
Appl. No.:
11/313085
Inventors:
Lordson L. Yue - Foster City CA, US
Vimal S. Parikh - Fremont CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G09G 5/00
G06T 1/20
US Classification:
345620, 345619, 345506
Abstract:
An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit that is configured to issue an initial set of outputs based on execution of a set of clipping operations. The graphics processing apparatus also includes a control unit that is connected to the clipping unit. The control unit is configured to preserve an initial execution state of the clipping unit in response to an initial command for context switching, and the initial execution state is preserved based on a number of the initial set of outputs.

Apparatus, System, And Method For Clipping Graphics Primitives With Respect To A Clipping Plane

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US Patent:
7439988, Oct 21, 2008
Filed:
Dec 5, 2005
Appl. No.:
11/295200
Inventors:
Vimal S. Parikh - Fremont CA, US
Henry Packard Moreton - Woodside CA, US
Lordson L. Yue - Foster City CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G09G 5/00
US Classification:
345620, 345619, 345622
Abstract:
Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a clipping module includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation that is defined with respect to a clipping plane. The clipping engine is configured to clip the graphics primitive with respect to the clipping plane based on the canonical representation.
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Lordson L Yue from Los Altos, CA, age ~61 Get Report