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Cheisan J Yue

from Austin, TX
Age ~70
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Also known as:
Jerry Yue
Related to:
Monica Yue, 31Joshua D Yue, 28Liching Yue, 68
Connected to:
Allan W Yue, 37Ann S Yue, 84Bingfang Yue, 55Changbiao Yue, 74Darren Yue, 36Fan T Yue, 58Gene M Yue, 66Guosen Yue, 52Hai Yue, 42Hao L Yue, 86

Cheisan Yue Phones & Addresses

  • Austin, TX
  • 1764 Skillman Ave W, Saint Paul, MN 55113
  • 1434 Bussard Ct, Saint Paul, MN 55112 (651) 728-3996
  • New Brighton, MN
  • Minneapolis, MN

Publications

Us Patents

Formation Of A Frontside Contact On Silicon-On-Insulator Substrate

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US Patent:
6576508, Jun 10, 2003
Filed:
Aug 26, 2002
Appl. No.:
10/227744
Inventors:
Paul S. Fechner - Plymouth MN
Cheisan Yue - Roseville MN
Assignee:
Honeywell International Inc - Morristown NJ
International Classification:
H01L 218242
US Classification:
438243, 438149, 438152, 438717, 438759
Abstract:
A method of forming a frontside contact to a Silicon-On-Insulator (SOI) wafer is described. A connection polysilicon connects a silicon substrate layer to a contact plug. This connection provides a means to ground or bias the bottom substrate of the SOI wafer. Spacers may be added to provide additional doping.

Frontside Contact On Silicon-On-Insulator Substrate

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US Patent:
6603166, Aug 5, 2003
Filed:
Nov 27, 2001
Appl. No.:
09/995400
Inventors:
Paul S. Fechner - Plymouth MN
Cheisan Yue - Roseville MN
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H01L 27108
US Classification:
257301, 438149, 438152, 438243, 438717
Abstract:
A method of forming a frontside contact to a Silicon-On-Insulator (SOI) wafer is described. A connection polysilicon connects a silicon substrate layer to a contact plug. This connection provides a means to ground or bias the bottom substrate of the SOI wafer. Spacers may be added to provide additional doping.

Gate Length Control For Semiconductor Chip Design

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US Patent:
6674108, Jan 6, 2004
Filed:
Dec 20, 2000
Appl. No.:
09/745239
Inventors:
Cheisan J. Yue - Roseville MN
Eric E. Vogt - Minneapolis MN
Todd N. Handeland - New Hope MN
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H01L 2976
US Classification:
257288, 257379, 257380, 257381
Abstract:
A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of the second polysilicon area comprises contacts of the semiconductor device. Metal covers the polysilicon contacts.

Gate Length Control For Semiconductor Chip Design

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US Patent:
6939758, Sep 6, 2005
Filed:
Jul 31, 2003
Appl. No.:
10/631596
Inventors:
Cheisan J. Yue - Roseville MN, US
Eric E. Vogt - Minneapolis MN, US
Todd N. Handeland - New Hope MN, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H01L021/302
H01L021/8234
US Classification:
438238, 438705
Abstract:
A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of the second polysilicon area comprises contacts of the semiconductor device. Metal covers the polysilicon contacts.

Low Loss Contact Structures For Silicon Based Optical Modulators And Methods Of Manufacture

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US Patent:
7149388, Dec 12, 2006
Filed:
Aug 10, 2004
Appl. No.:
10/915607
Inventors:
Thomas Keyser - Plymouth MN, US
Cheisan J. Yue - Roseville MN, US
Assignee:
Honeywell International, Inc. - Morristown NJ
International Classification:
G02B 6/42
G02F 1/295
US Classification:
385 40, 385 8
Abstract:
The present invention provides silicon based thin-film structures that can be used to form high frequency optical modulators. Devices of the invention are formed as layered structures that have a thin-film dielectric layer, such as silicon dioxide, sandwiched between silicon layers. In one aspect of the invention an electrical contact structure is provided. The electrical contact structure comprises a connecting portion that electrically connects an active region of at least one of the silicon layers to a contact portion of the electrical contact structure.

Varactor With Improved Tuning Range

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US Patent:
7169679, Jan 30, 2007
Filed:
Jan 7, 2002
Appl. No.:
10/040395
Inventors:
Cheisan J. Yue - Roseville MN, US
Mohammed A. Fathimulla - Ellicott City MD, US
Eric E. Vogt - Maple Grove MN, US
William L. Larson - Eden Prairie MN, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H01L 21/20
H01L 21/36
H01L 21/336
US Classification:
438379, 438197, 438479
Abstract:
A varactor has a plurality of alternating P− wells and N+ regions formed in a silicon layer. Each of the P− wells forms a first N+/P− junction with the N+ region on one of its side and a second N+/P− junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P− wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.

Silicon-Insulator-Silicon Thin-Film Structures For Optical Modulators And Methods Of Manufacture

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US Patent:
7177489, Feb 13, 2007
Filed:
Aug 10, 2004
Appl. No.:
10/915299
Inventors:
Thomas Keyser - Plymouth MN, US
Cheisan J. Yue - Roseville MN, US
Bradley J. Larsen - Mound MN, US
Assignee:
Honeywell International, Inc. - Morristown NJ
International Classification:
G02B 1/01
G02B 6/10
H01L 21/302
US Classification:
385 1, 385129, 438719
Abstract:
The present invention provides silicon based thin-film structures that can be used to form high frequency optical modulators. Devices of the invention are formed as layered structures that have a thin-film dielectric layer, such as silicon dioxide, sandwiched between silicon layers. The silicon layers have high free carrier mobility. In one aspect of the invention a high mobility silicon layer can be provided by crystallizing an amorphous silicon layer. In another aspect of the invention, a high mobility silicon layer can be provided by using selective epitaxial growth and extended lateral overgrowth thereof.

Method And Apparatus For An Integrated Gps Receiver And Electronic Compassing Sensor Device

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US Patent:
7206693, Apr 17, 2007
Filed:
Jan 8, 2004
Appl. No.:
10/754947
Inventors:
William F. Witcraft - Minneapolis MN, US
Hong Wan - Plymouth MN, US
Cheisan J. Yue - Roseville MN, US
Tamara K. Bratland - Plymouth MN, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
G01C 21/26
US Classification:
701207, 701217
Abstract:
At least one magnetic field sensing device and GPS receiver integrated in a discrete, single-chip package, and a method of manufacture for the same. Rather than requiring at least two separate chips to be used to realize GPS positioning and compassing capabilities in a single device, an integrated, single chip solution can be used. A single chip integration of a GPS receiver and at least one magnetic field sensing device can reduce the physical space required to provide positioning and electronic compassing capabilities in a single device, and therefore allow such devices to be smaller, lighter, and possibly more portable.
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Cheisan J Yue from Austin, TX, age ~70 Get Report