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Lancelot Kwong Phones & Addresses

  • 43275 Paseo Padre Pkwy, Fremont, CA 94539 (510) 651-6231
  • 587 Big Foot Ct, Fremont, CA 94539 (510) 651-6231
  • Sacramento, CA
  • Oakley, CA
  • Brentwood, CA
  • Milpitas, CA
  • San Jose, CA
  • Melbourne, FL
  • Alameda, CA
  • 43275 Paseo Padre Pkwy, Fremont, CA 94539

Work

Position: Technicians and Related Support Occupations

Education

Degree: High school graduate or higher

Publications

Us Patents

Memory With Active Mode Back-Bias Voltage Control And Method Of Operating Same

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US Patent:
20090213641, Aug 27, 2009
Filed:
Feb 22, 2008
Appl. No.:
12/035601
Inventors:
Heechoul Park - San Jose CA, US
Song Chin Kim - San Jose CA, US
Lancelot Y. Kwong - Fremont CA, US
Wilson Fai Chin - Cupertino CA, US
International Classification:
G11C 11/00
G11C 7/00
G11C 8/00
G11C 5/14
US Classification:
365154, 36518909, 365226, 36523001
Abstract:
Data storage cells of a static random access memory array are selectively provided with back-bias voltages to reduce current leakage during an active mode of operation. Circuitry electrically connected with the array receives control signals and provides the back-bias voltages to certain idle data storage cells of the array based on the control signals.

Write And Read Assist Circuit For Sram With Power Recycling

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US Patent:
20090303819, Dec 10, 2009
Filed:
Jun 5, 2008
Appl. No.:
12/133808
Inventors:
Heechoul Park - San Jose CA, US
Song Kim - San Jose CA, US
Lancelot Kwong - Fremont CA, US
Assignee:
SUN MICROSYSTEMS, INC. - SANTA CLARA CA
International Classification:
G11C 7/00
G11C 5/14
G11C 8/00
US Classification:
365203, 365226, 36523006
Abstract:
A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge storage, a precharge switch, a write enable switch, and column decoder. The cell voltage level switch is connected to a low power supply and a high power supply and has two states of operation: a write operation state and a read operation state. For each state of operation, the voltage level switch selectively provides a power supply if a column has been selected or if the operation is a read or write. The recycle charge storage stores excess charge from SRAM cells after a read operation or after a write operation in unselected columns. After the read or write operation, the recycle charge storage discharges excess charge to the bitlines during bitline precharging.

Memory Circuit March Testing

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US Patent:
20190235019, Aug 1, 2019
Filed:
Jan 29, 2018
Appl. No.:
15/882674
Inventors:
- Redwood City CA, US
Lancelot Kwong - Fremont CA, US
International Classification:
G01R 31/3177
G01R 31/317
Abstract:
Embodiments include novel approaches for scan-based device testing using a march controller. A march data store can have sets of march element data stored thereon, each defining a respective march element of a march test sequence. A march select register can select each stored set of march element data according to the predefined march test sequence, and a march data loader can iteratively and sequentially output each set of march element data selected by the march select register. A memory built-in self-test controller can generate, in response to receiving each set of march element data output by the march controller, test stimulus data corresponding to the received set of march element data. The test stimulus data can input to a scan chain of the integrated circuit under test, and response data can be captured from the scan chain and assessed to determine whether the integrated circuit passed the test.
Lancelot Y Kwong from Fremont, CA, age ~68 Get Report