US Patent:
20080151513, Jun 26, 2008
Inventors:
Joseph Parchesky - Dallas TX, US
International Classification:
H05K 1/00
H05K 7/00
H05K 7/10
Abstract:
The board real estate consumed by a number of blocking capacitors, which are connected to the top surface of a printed circuit board to isolate circuits with different DC voltage levels while permitting a high frequency signal to pass through, and a number of metal-plated holes, which are associated with the blocking capacitors, is substantially reduced by forming the capacitors and metal-plated holes between the pins of a high-frequency connector. Forming the metal-plated holes between the pins of the high-frequency connector reduces the number of metal-plated holes in the signal path. This, in turn, substantially reduces the parasitic capacitive and inductive elements, thereby substantially improving the signal integrity of the PCB design.