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Jianjun Jia

from Cedar Park, TX
Age ~43
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Also known as:
Ianjun V Jia, Jia Jianjun
Connected to:
Anna Jia, 37Chang L Jia, 68Daniel X Jia, 61Daphne Jia, 64Eric Jia, 30Hongwei Jia, 51Judy J Jia, 40Julie W Jia, 35Kai Jia, 56Kelly Q Jia, 37

Jianjun Jia Phones & Addresses

  • Cedar Park, TX
  • Austin, TX
  • 43297 Livermore Cmn, Fremont, CA 94539
  • San Jose, CA
  • Ellicott City, MD
  • Baltimore, MD
  • Irvine, CA

Work

Company: Space telescope science institute - Baltimore, MD

Education

School / High School: Hong Kong University- Hong Kong, Hong Kong Island 2003 Specialities: M.Phil. in Department of Physics

Skills

Semiconductors • Soc

Industries

Semiconductors

Resumes

Resumes

Jianjun Jia Photo 1

Senior Staff R And D Engineer

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Synopsys
Senior Staff R and D Engineer
Arm
Senior Principal Engineer
Arm Jan 2006 - Apr 2015
Manager of Product Engineering
Artisan-Arm Nov 2003 - Dec 2005
Staff Product Engineer
Supertex Oct 2000 - Nov 2003
Manager, Process Integration
Education:
University of Tennessee, Knoxville 1986 - 1991
Doctorates, Doctor of Philosophy, Physics, Philosophy
Skills:
Semiconductors
Soc
Jianjun Jia Photo 2

Jianjun Jia Baltimore, MD

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Work:
Space Telescope Science Institute
Baltimore, MD
2006 to 2007
Hong Kong University, Hong Kong, China

2003 to 2005
Education:
Hong Kong University
Hong Kong, Hong Kong Island
2003 to 2005
M.Phil. in Department of Physics
Nanjing University
1999 to 2003
B.S. in Department of Astronomy
Johns Hopkins University
Baltimore, MD
Ph.D. in Department of Physics and Astronomy
People's Fellowship of Nanjing University

Publications

Us Patents

Pattern Placement Error Aware Optimization

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US Patent:
20170082927, Mar 23, 2017
Filed:
Mar 3, 2015
Appl. No.:
15/126234
Inventors:
- Veldhoven, NL
Jianjun JIA - Santa Clara CA, US
Xiaofeng LIU - Santa Clara CA, US
Youping ZHANG - Santa Clara CA, US
Assignee:
ASML Netherlands B.V. - Veldhoven
International Classification:
G03F 7/20
Abstract:
A method to improve a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus, the method including: computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied. The multi-variable cost function may be a function of one or more pattern shift errors. Reconfiguration of the characteristics may be under one or more constraints on the one or more pattern shift errors.
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Jianjun Jia from Cedar Park, TX, age ~43 Get Report