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James P Shiely

from Portland, OR
Age ~53

James Shiely Phones & Addresses

  • Portland, OR
  • 7200 189Th Ave, Beaverton, OR 97007 (503) 591-9141
  • Hillsboro, OR
  • 201 Conner Dr, Chapel Hill, NC 27514 (919) 918-7624
  • 920 Lake St, Prescott, WI 54021 (715) 262-3566 (651) 208-2077
  • Apache Junction, AZ

Professional Records

Lawyers & Attorneys

James Shiely Photo 1

James F. Shiely, Saint Paul MN - Lawyer

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Address:
Gearin & Shiely Pa
500 Degree Of Honor Bldg 325 Cedar St, Saint Paul, MN 55101
(651) 227-7577 (Office)
Licenses:
Wisconsin - Good Standing 1982
Education:
University of Minnesota Law School
Graduated - 1971
Languages:
English
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James F Shiely Jr. - Lawyer

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Address:
325 Cedar St, Ste 500 500 Degree Of Honor Bldg, St Paul, MN 55101
Licenses:
Minnesota - Authorized to practice 1971
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James Shiely - Lawyer

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Address:
325 Cedar St
Phone:
(651) 227-7577 (Phone), (651) 223-5111 (Fax)
Jurisdiction:
Minnesota
Memberships:
Minnesota State Bar

Resumes

Resumes

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Engineering Director

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Location:
Portland, OR
Industry:
Computer Software
Work:
Synopsys
Engineering Director

Synopsys Aug 2007 - Dec 2015
Director, Research and Development

Avant and Synopsys Aug 1999 - Aug 2007
Various

Duke University 1993 - 1999
Research Assistant
Education:
Duke University 1993 - 1999
Master of Science, Doctorates, Masters, Doctor of Philosophy, Electrical Engineering
University of Notre Dame 1989 - 1993
Bachelors, Bachelor of Science, Electrical Engineering
St. Thomas Academy 1985 - 1989
Skills:
Semiconductors
Eda
Software Development
Simulations
Algorithms
Software Engineering
C
Distributed Systems
C++
Debugging
Perl
Ic
Asic
Research and Development
Linux
Tcl
Image Processing
Testing
Agile Methodologies
Multithreading
Embedded Systems
Embedded Software
Software Design
Unix
Object Oriented Design
Shell Scripting
Python
R&D
Matlab
Integrated Circuits
Machine Learning
Management
Engineering Management
Research
Artificial Neural Networks
Artificial Intelligence
Interests:
Nanoscale Patterning
Semiconductor Manufacturing
Software Architecture
Computer Architecture
Image Processing
Global Teams Software Development
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James Shiely

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James Shiely

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James Shiely

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Publications

Us Patents

Method And Apparatus For Identifying A Manufacturing Problem Area In A Layout Using A Process-Sensitivity Model

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US Patent:
7251807, Jul 31, 2007
Filed:
Feb 24, 2005
Appl. No.:
11/065409
Inventors:
James P. Shiely - Aloha OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 21, 716 19, 716 20
Abstract:
One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more arbitrary process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then identifies a problem area in the mask layout using the process-sensitivity model. Identifying the problem area allows it to be corrected, which improves the manufacturability of the mask layout. Moreover, using the process-sensitivity model to identify the problem area reduces the computational time required to identify the problem area.

Method And Apparatus For Correcting 3D Mask Effects

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US Patent:
7308673, Dec 11, 2007
Filed:
Jan 10, 2005
Appl. No.:
11/033415
Inventors:
Qiliang Yan - Hillsboro OR, US
James P. Shiely - Aloha OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
G03F 1/00
US Classification:
716 21, 716 19, 430 5
Abstract:
One embodiment of the present invention provides a system that improves lithography performance by correcting for 3D mask effects. During operation the system receives a mask layout that contains etched regions, called shifters, which can have a phase shift relative to other regions. Next, the system chooses a shifter in the mask layout. The system then corrects for 3D mask effects by, iteratively, (a) selecting a region within the shifter, (b) adjusting the phase shift of the selected region in a simulation model to account for 3D mask effects, and (c) modifying the shape of the shifter based on the difference between a desired pattern and a simulated pattern generated using the simulation model.

Method And Apparatus For Identifying A Problem Edge In A Mask Layout Using An Edge-Detecting Process-Sensitivity Model

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US Patent:
7320119, Jan 15, 2008
Filed:
May 6, 2005
Appl. No.:
11/124328
Inventors:
James P. Shiely - Aloha OR, US
Qiliang Yan - Hillsboro OR, US
Benjamin D. Painter - Tigard OR, US
Assignee:
Synopsys, Inc. - Mountain View
International Classification:
G06F 17/50
US Classification:
716 21, 716 19, 716 20, 430 5, 430 30
Abstract:
One embodiment of the present invention provides a system that identifies a problem edge in a mask layout which is likely to have manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more process conditions that are different from nominal process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then computes an edge-detecting process-sensitivity model by convolving the process-sensitivity model with an edge-detecting function which can be used to detect edges in an image. Next, the system identifies a problem edge in the mask layout using the edge-detecting process-sensitivity model.

Method And Apparatus For Improving Depth Of Focus During Optical Lithography

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US Patent:
7494751, Feb 24, 2009
Filed:
Jan 27, 2005
Appl. No.:
11/045966
Inventors:
James P. Shiely - Aloha OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G03F 9/00
US Classification:
430 30, 430 5, 716 21
Abstract:
One embodiment of the present invention provides a system that improves the depth of focus during an optical lithography process. During operation, the system receives a mask layout. The system then selects an edge in the mask layout. Next, the system adds a notch to the edge to improve the depth of focus by helping to maintain a critical dimension associated with the edge as the optical lithography process drifts out of focus. Note that adding a notch to the edge adds a high spatial-frequency component to the mask layout. This high spatial-frequency component degrades as the optical lithography process drifts out of focus. This degradation causes the mask layout to allow more light into the pattern, which helps maintain the critical dimension, thereby improving depth of focus.

Method And Apparatus For Identifying A Manufacturing Problem Area In A Layout Using A Gradient-Magnitude Of A Process-Sensitivity Model

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US Patent:
7784018, Aug 24, 2010
Filed:
May 8, 2007
Appl. No.:
11/801350
Inventors:
James P. Shiely - Aloha OR, US
Qiliang Yan - Hillsboro OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 19, 716 20, 716 21, 430 5, 430 30
Abstract:
One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal (e. g. , optimal) process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more arbitrary (e. g. , non-optimal) process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then computes a gradient-magnitude of the process-sensitivity model. Next, the system identifies a problem area in the mask layout using the gradient-magnitude of the process-sensitivity model. Note that identifying the problem area allows it to be corrected, which improves the manufacturability of the mask layout.

Method And System For Correlating Physical Model Representation To Pattern Layout

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US Patent:
7933471, Apr 26, 2011
Filed:
Mar 9, 2007
Appl. No.:
11/716511
Inventors:
Jianliang Li - Hillsboro OR, US
Qiliang Yan - Portland OR, US
James P. Shiely - Aloha OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06K 9/00
G06K 9/36
G06K 9/64
US Classification:
382279, 382276, 382278, 382144
Abstract:
One embodiment of the present invention provides a system that reduces computational complexity in simulating an image resulting from an original mask and an optical transmission system. During operation, the system obtains a set transmission cross coefficient (TCC) kernel functions based on the optical transmission system, and obtains a set of transmission functions for a representative pattern which contains features representative of the original mask. The system constructs a new set of kernel functions based on the TCC kernel functions and the transmission functions for the representative pattern, wherein responses to the new kernel functions in a resulting image corresponding to the representative pattern are substantially uncorrelated with one another. The system further produces an intensity distribution of a resulting image corresponding to the original mask based on the new kernel functions, thereby facilitating prediction of a layout that can be produced from the original mask.

Method And System For Performing Lithography Verification For A Double-Patterning Process

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US Patent:
8132128, Mar 6, 2012
Filed:
Oct 31, 2008
Appl. No.:
12/263278
Inventors:
Hua Song - San Jose CA, US
Lantian Wang - Fremont CA, US
Gerard Terrence Luk-Pat - Sunnyvale CA, US
James P. Shiely - Aloha OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
G06F 19/00
US Classification:
716 51, 700121
Abstract:
One embodiment of the present invention provides a system that performs lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout. During operation, the system starts by receiving a first mask which is used in a first lithography step of the double-patterning process, and a second mask which is used in a second lithography step of the double-patterning process. Note that the first mask and the second mask are obtained by partitioning the mask layout. Next, the system receives an evaluation point on the mask layout. The system then determines whether the evaluation point is exclusively located on a polygon of the first mask, exclusively located on a polygon of the second mask, or located elsewhere. The system next computes a printing indicator at the evaluation point for the mask layout based on whether the evaluation point is exclusively located on a polygon of the first mask or exclusively located on a polygon of the second mask.

Non-Linear Rasterized Contour Filters

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US Patent:
8291353, Oct 16, 2012
Filed:
Aug 29, 2011
Appl. No.:
13/220600
Inventors:
Zhijie Deng - Portland OR, US
James Patrick Shiely - Portland OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 55, 716 50, 716 52, 716 53, 716 54
Abstract:
A system includes a conversion module that preserves the shape of a contour when converting an image to a different resolution. The conversion module receives a first image and divides the first image into regions of pixel values. For each region, a contribution of the region to the pixel values in the second image is determined. The contribution is selected from a set of pre-determined contributions that are a nonlinear function of the values in the region, and the selection is made based at least in part on the values in the region. The contributions are accumulated together to generate a second image. The conversion module may be, for example, part of a design flow for an integrated circuit that connects a mask simulation stage with an optical simulation stage.
James P Shiely from Portland, OR, age ~53 Get Report