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Derek F Iwamoto

from Sunnyvale, CA
Age ~58
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Also known as:
Derek Fujio Iwamoto, Derek Te Iwamoto
Related to:
Kimberly A Iwamoto, 43Harold BrownSusanna Brown, 67Arthur BrownArthur Brown, 70Mary Brown
Connected to:
Alejandro K Iwamoto, 55Alyson Iwamoto, 38Cindy K Iwamoto, 60Dennis T Iwamoto, 95Gary K Iwamoto, 67Henry T Iwamoto, 87Joyce M Iwamoto, 65Linda M Iwamoto, 83Marc T Iwamoto, 49

Derek Iwamoto Phones & Addresses

  • Sunnyvale, CA
  • Honolulu, HI
  • 883 Knollfield Way, San Jose, CA 95136 (408) 266-8857 (408) 961-1237
  • 1046 Mokapu Rd, Kailua, HI 96734 (808) 254-1013
  • Modesto, CA
  • Austin, TX
  • Santa Clara, CA
  • 1029 Ranere Ct, Sunnyvale, CA 94087

Work

Company: The queen's medical center Position: Applications development specialist

Industries

Hospital & Health Care

Resumes

Resumes

Derek Iwamoto Photo 1

Applications Development Specialist

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Location:
Honolulu, HI
Industry:
Hospital & Health Care
Work:
The Queen's Medical Center
Applications Development Specialist

Publications

Us Patents

Method And Apparatus For Improved Memory Core Testing

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US Patent:
6865701, Mar 8, 2005
Filed:
Mar 29, 2001
Appl. No.:
09/823148
Inventors:
Lynn R. Youngs - Cupertino CA, US
Derek F. Iwamoto - San Jose CA, US
Assignee:
Apple Computer, Inc. - Cupertino CA
International Classification:
G11C029/00
US Classification:
714718, 714 30, 365201
Abstract:
A memory unit is described that has a controller coupled to a memory core through an interface circuit. The interface circuit has a test data input that receives test data from the controller. The interface circuit also has a system data input that receives data from a system. The interface circuit has a data output that is coupled to a data input of the memory core.

Method And Apparatus For Forming And Dispatching Instruction Groups Based On Priority Comparisons

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US Patent:
7114058, Sep 26, 2006
Filed:
Dec 31, 2001
Appl. No.:
10/038383
Inventors:
Sushma Shrikant Trivedi - Sunnyvale CA, US
Joseph P. Bratt - San Jose CA, US
Jack Benkual - Cupertino CA, US
Ronald Ray Hochsprung - Los Gatos CA, US
Derek Fujio Iwamoto - San Jose CA, US
Assignee:
Apple Computer, Inc. - Cupertino CA
International Classification:
G06F 9/30
US Classification:
712215
Abstract:
Methods and apparatuses for dispatching instructions executed by at least one functional unit of a data processor, each one of the instructions having a corresponding priority number, in a data processing system having at least one host processor with host processor cache and host memory are described herein. In one aspect of the invention, an exemplary method includes receiving a next instruction from an instruction stream, examining a current instruction group to determine if the current instruction group is completed, adding the next instruction to the current instruction group if the current instruction group is not completed, and dispatching the current instruction group if the current instruction group is completed.

Method And Apparatus For Data Processing

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US Patent:
7305540, Dec 4, 2007
Filed:
Dec 31, 2001
Appl. No.:
10/038742
Inventors:
Sushma Shrikant Trivedi - Sunnyvale CA, US
Joseph P. Bratt - San Jose CA, US
Jack Benkual - Cupertino CA, US
Vaughn Todd Arnold - Scotts Valley CA, US
Derek Fujio Iwamoto - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 15/76
G06F 15/17
US Classification:
712 3, 712 33, 712 38
Abstract:
Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling the host memory comprising DRAM memory, the memory controller coupled to the chip interconnect, a scalar processing unit coupled the chip interconnect wherein the scalar processing unit is capable of executing instructions to perform scalar data processing, a vector processing unit coupled the chip interconnect wherein the vector processing unit is capable of executing instructions to perform vector data processing, and an input/output (I/O) interface coupled to the chip interconnect wherein the I/O interface receives/transmits data from/to the scalar and/or vector processing units.

Memory Power Reduction In A Sleep State

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US Patent:
20110185208, Jul 28, 2011
Filed:
Sep 30, 2010
Appl. No.:
12/895702
Inventors:
Derek Iwamoto - Sunnyvale CA, US
Steven J. Sfarzo - Los Gatos CA, US
Ryan Schmidt - San Jose CA, US
Derrick Carty - Los Altos CA, US
Keith Cox - Sunnyvale CA, US
Assignee:
APPLE INC. - Cupertino CA
International Classification:
G06F 1/32
US Classification:
713323
Abstract:
A data processing system that uses memory power reduction in a sleep state. The system can include a volatile memory and at least one data input peripheral and a logic circuit that is configured to manage power consumption of the data processing system for a sleep of the system. The logic circuit can be coupled to the volatile memory and can be configured to turn off power to the volatile memory in response to an event, occurring during the sleep state, but to otherwise remain in the sleep state. The sleep state can be an ACPI complaint S3 sleep state in which the volatile memory, such as DRAM, is powered off after a period of user inactivity during the S3 sleep state.

Memory Controller Chipset

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US Patent:
6822654, Nov 23, 2004
Filed:
Dec 31, 2001
Appl. No.:
10/038700
Inventors:
Sushma Shrikant Trivedi - Sunnyvale CA
Joseph P. Bratt - San Jose CA
Jack Benkual - Cupertino CA
Vaughn Todd Arnold - Scotts Valley CA
Yutaka Takahashi - Cupertino CA
Steven Todd Weybrew - Portland OR
Derek Fujio Iwamoto - San Jose CA
David Ligon - Mountain View CA
Assignee:
Apple Computer, Inc. - Cupertino CA
International Classification:
G06F 1314
US Classification:
345520, 345519, 345531, 345557, 345568
Abstract:
At least one chip of a chipset in a computer system having at least one host processor and a host memory are described herein. In one aspect of the invention, an exemplary chip includes an interconnect, a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access, a host interface coupled to the interconnect, the host interface providing access to the host processor, and a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media.

Aggregating Multiple Data Streams On A Communication Link

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US Patent:
20220353736, Nov 3, 2022
Filed:
Jul 19, 2021
Appl. No.:
17/379088
Inventors:
- Cupertino CA, US
Venkatesh Rajendran - San Jose CA, US
Derek Fujio Iwamoto - Sunnyvale CA, US
International Classification:
H04W 28/06
H04W 76/10
H04W 4/18
H04W 56/00
Abstract:
A host device establishes a wireless communication link with a client device, and implements a wired communication standard on the link to transfer a first data stream. To increase data throughput while complying with the standard, the host device replaces synchronizing information in a packet to be sent during a first synchronizing frame with configuration information indicating that packet exchange data of a second data stream is to be sent or received during a second synchronizing frame. The host device sends or receives the packet exchange data of the second data stream to or from the client device during the second synchronizing frame via the wireless communication link. The host device may send or receive the packet exchange data of the second data stream during delays or idle periods between sending and/or receiving packets of the first data stream via the wireless communication link according to the wired communication standard.

Wireless Communication Devices

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US Patent:
20230084538, Mar 16, 2023
Filed:
Dec 7, 2021
Appl. No.:
17/544262
Inventors:
- Cupertino CA, US
Annie Manuja - Sunnyvale CA, US
Christopher D. Guichet - Mountain View CA, US
Erik G. de Jong - San Francisco CA, US
Jorge L. Rivera Espinoza - San Jose CA, US
Patrick J. Crowley - San Jose CA, US
Steven C. Roach - Martinez CA, US
Venkatesh Rajendran - San Jose CA, US
William C. Lukens - San Francisco CA, US
Woojin Jung - San Mateo CA, US
Yue Chen - San Jose CA, US
Zhiwei Gu - Cupertino CA, US
Derek Iwamoto - Sunnyvale CA, US
Siddharth Nangia - San Francisco CA, US
Scott D. Morrison - Austin TX, US
Kevin A. Klenk - Sunnyvale CA, US
Neeloy Roy - San Francisco CA, US
International Classification:
H01Q 1/24
H01Q 1/22
H01Q 9/04
H01Q 1/52
Abstract:
A wireless communication system may include an electronic device having a wireless communication module. The wireless communication module may include an antenna radiating element on a first surface, a ground ring surrounding the antenna radiating element on the first surface, and a radio component mounted to a second surface. The wireless communication module may be incorporated into a system package that also includes other components. Encapsulation material may cover the wireless communication module and other components. A shielding material may cover the encapsulation material and be coupled to the ground ring. An opening in the shielding material may be aligned with the antenna radiating element. If desired, the wireless communication system may include external equipment having a wireless communication module communicatively coupled to the wireless communication module to convey firmware testing, debugging, restore, and/or other data.

Interface Emulator Using Fifos

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US Patent:
20170277648, Sep 28, 2017
Filed:
Jun 13, 2017
Appl. No.:
15/621265
Inventors:
- Cupertino CA, US
Josh P. de Cesare - Campbell CA, US
Brijesh Tripathi - Los Altos CA, US
Derek Iwamoto - San Francisco CA, US
Shane J. Keil - San Jose CA, US
International Classification:
G06F 13/42
G06F 13/10
G06F 13/40
G06F 13/38
Abstract:
An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.
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Derek F Iwamoto from Sunnyvale, CA, age ~58 Get Report