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Daniel Kershaw

from Austin, TX
Age ~60
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Also known as:
Danny Kershaw
Connected to:
Abigail Kershaw, 29Anna C Kershaw, 68Barbara A Kershaw, 56Christie E Kershaw, 29Damon Kershaw, 60Darlena Kershaw, 35Edward J Kershaw, 66Elaine T Kershaw, 90Eleanor Kershaw, 89Elliott L Kershaw, 76

Daniel Kershaw Phones & Addresses

  • Austin, TX
  • San Jose, CA
  • 750 University Ave, Los Gatos, CA 95032
  • Miami Gardens, FL

Publications

Us Patents

Result Partitioning Within Simd Data Processing Systems

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US Patent:
7668897, Feb 23, 2010
Filed:
Jun 16, 2003
Appl. No.:
10/461880
Inventors:
Daniel Kershaw - Austin TX, US
Assignee:
ARM Limited - Cambridge
International Classification:
G06F 7/38
US Classification:
708513, 712 22
Abstract:
Within a processor providing single instruction multiple data (SIMD) type operation, single data processing instructions can serve to control processing logic to perform SIMD-type processing operations upon multiple independent input values to generate multiple independent result values having a greater data width than the corresponding input values. A repartitioner (FIG. ) in the form of appropriately controlled multiplexers serves to partition these result data values into high order bit portions and low order bit portions that are stored into separate registers. The required SIMD width preserved result values can be read from the desired high order result register or low order result register without further processing being required. Furthermore, the preservation of the full result facilitates improvements in accuracy, such as over extended accumulate operations and the like.

Data Element Size Control Within Parallel Lanes Of Processing

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US Patent:
20050125631, Jun 9, 2005
Filed:
Jul 13, 2004
Appl. No.:
10/889471
Inventors:
Dominic Symes - Cambridge, GB
Simon Ford - Cambridge, GB
Daniel Kershaw - Austin TX, US
David Seal - Cambridge, GB
Assignee:
ARM LIMITED - Cambridge
International Classification:
G06F015/00
US Classification:
712022000
Abstract:
Within a SIMD processor data processing instructions are provided which specify parallel lanes of processing to be performed upon respective data elements. The data elements are permitted to vary in size whilst the number of processing lanes remain constant. Thus, the destination register size for a multiplication may be double the source register size.

Vector By Scalar Operations

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US Patent:
20050125636, Jun 9, 2005
Filed:
Jul 13, 2004
Appl. No.:
10/889316
Inventors:
Simon Ford - Cambridge, GB
Dominic Symes - Cambridge, GB
Daniel Kershaw - Austin TX, US
Andrew Rose - Cambridge, GB
Assignee:
ARM LIMITED - Cambridge
International Classification:
G06F015/00
US Classification:
712221000, 712022000
Abstract:
A data processing apparatus is disclosed. The apparatus comprises a register data store comprising a plurality of registers. The apparatus further comprises a data processor operable to perform in parallel a data processing operation on data elements; and decode logic responsive to a single vector-by-scalar instruction to control the data processor so as to specify one of the plurality of registers as a first source register operable to store a plurality of source data elements, to specify another of the plurality of registers as a second source register operable to store a plurality of selectable data elements, to select one of said selectable data elements as a scalar operand and to perform a vector-by-scalar operation in parallel on the source data elements, each vector-by-scalar operation causing a resultant data element to be generated from a source data element and the scalar operand. By providing a source register which contains selectable data elements it is possible to select one of those data elements as a scalar operand and to perform multiple vector-by-scalar operations in parallel using the same scalar operand on all source data elements.

Data Shift Operations

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US Patent:
20050125638, Jun 9, 2005
Filed:
Jul 13, 2004
Appl. No.:
10/889365
Inventors:
Simon Ford - Cambridgeshire, GB
Dominic Symes - Cambridge, GB
Daniel Kershaw - Austin TX, US
Assignee:
ARM LIMITED - Cambridge
International Classification:
G06F009/00
US Classification:
712221000, 712022000
Abstract:
A data processing apparatus and method. The data processing apparatus comprising: a register data store operable to store data elements; an instruction decoder operable to decode a shift instruction; a data processor operable to perform data processing operations controlled by said instruction decoder wherein: in response to said decoded shift instruction, said data processor is operable to specify within said register data store, one or more source registers operable to store a plurality of source data elements of a first size, and one or more destination registers operable to store a corresponding plurality of resultant data elements of a second size, said second size not being equal to said first size; and to perform the following operations in parallel on said plurality of source data elements to produce said corresponding plurality of resultant data elements: shift each of said plurality of source data elements a specified number of places; form at least a part of each of said resultant data elements from information derived from at least a portion of a corresponding one of said plurality of source data elements; store said resultant data elements in said destination register.

Saturating Shift Mechanisms Within Data Processing Systems

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US Patent:
20050210089, Sep 22, 2005
Filed:
Mar 19, 2004
Appl. No.:
10/804181
Inventors:
Daniel Kershaw - Austin TX, US
Micah McDaniel - Austin TX, US
Assignee:
ARM LIMITED - Cambridge
International Classification:
G06F007/00
US Classification:
708209000
Abstract:
A saturating shifter is provided which operates to detect in parallel with a shifting operation whether the result of that shifting operation will require saturating. If saturation is required, then the necessary saturating mask may be determined earlier and accordingly processing speed increased.

Polynomial And Integer Multiplication

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US Patent:
20050273485, Dec 8, 2005
Filed:
Jun 3, 2004
Appl. No.:
10/859597
Inventors:
Daniel Kershaw - Austin TX, US
Micah McDaniel - Austin TX, US
Assignee:
ARM LIMITED - Cambridge
International Classification:
G06F007/52
US Classification:
708700000
Abstract:
A method and apparatus for generating a plurality of concurrent significant bits forming at least a portion of a product from at least two partial products, the method comprising the following steps: for each of a plurality of said concurrent predetermined significant bits performing steps (i) to (iii): (i) performing an addition of bits of a predetermined significance from each of said plurality of partial products having a bit of said predetermined significance; (ii) forming an intermediate sum of said predetermined significance from the least significant bit of said additions; (iii) forming at least one intermediate carry of a higher significance from said higher significant bits of said sum; and detecting if said partial products are formed from integers or polynomials; and outputting said plurality of intermediate sum bits formed during steps (i) to (iii) as a plurality of product bits of corresponding significance in response to detection of polynomials; or combining said intermediate carrys and said intermediate sum bits with a same significance to produce a product bit of a corresponding significance in response to detection of integers, and outputting said combination as a plurality of product bits of corresponding significance.
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Daniel Kershaw from Austin, TX, age ~60 Get Report