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Bijan K Bhattacharyya

from Irvine, CA
Age ~73
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Also known as:
Bijan Tr Bhattacharyya, Bijan K Bhattachryya, Bijan Bhattach Yya, Bijan A
Phone and address:
17 Santa Comba, Irvine, CA 92606
(949) 651-1323
Related to:
Tuhin K Bhattacharyya, 35Tania Bhattacharyya, 37Kakoli Bhattacharyya, 67
Connected to:
Abhijit Bhattacheryya, 47Achyut K Bhattacharyya, 72Ajay Bhattacharyya, 39Ajit K Bhattacharyya, 89Ananda M Bhattacharyya, 93Anandaroop Bhattacharya, 50Aninda Bhattacharyya, 40Anita Bhattacharya, 67Anita Bhatta, 43Anwesha Bhattacharyya, 36

Bijan Bhattacharyya Phones & Addresses

  • 17 Santa Comba, Irvine, CA 92606 (949) 651-1323
  • Macungie, PA
  • Allentown, PA
  • Costa Mesa, CA
  • Newport Beach, CA
  • Austin, TX
  • 17 Santa Comba, Irvine, CA 92606

Work

Company: Conexant systems, inc., newport beach, ca Jan 1999 Position: Manager, analog mixed-signal design kit development, support, and methodology

Education

Degree: Ph.D. School / High School: Indiana University Bloomington 1977 to 1982 Specialities: Physics

Skills

IC • Spectre • Virtuoso • PDK Development • Cadence Skill • Semiconductors • Mixed Signal • Analog • CMOS • Cadence Virtuoso • Simulations • Circuit Simulators • Calibre • Virtuoso XL • Perl • unix • PLL • Silicon • VLSI • Unix • SoC • EDA • ASIC • Verilog

Industries

Semiconductors

Resumes

Resumes

Bijan Bhattacharyya Photo 1

Manager, Analog Mixed-Signal Design Kit Development, Support, And Methodology At Conexant Systems, Inc.

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Position:
Manager, Analog Mixed-Signal Design Kit Development, Support, and Methodology at Conexant Systems, Inc., Newport Beach, CA
Location:
Orange County, California Area
Industry:
Semiconductors
Work:
Conexant Systems, Inc., Newport Beach, CA since Jan 1999
Manager, Analog Mixed-Signal Design Kit Development, Support, and Methodology
Rockwell Semiconductor, Newport Beach, CA Jan 1996 - Dec 1998
Distinguished Engineer
AT&T Bell Laboratories, Allentown, PA Jan 1988 - Dec 1995
Member, Technical Staff
INMOS Corporation, Colorado Springs, CO May 1985 - Dec 1987
CAD/Device Engineer
University of Texas at Austin 1982 - 1985
Research Fellow
Education:
Indiana University Bloomington 1977 - 1982
Ph.D., Physics
Skills:
IC
Spectre
Virtuoso
PDK Development
Cadence Skill
Semiconductors
Mixed Signal
Analog
CMOS
Cadence Virtuoso
Simulations
Circuit Simulators
Calibre
Virtuoso XL
Perl
unix
PLL
Silicon
VLSI
Unix
SoC
EDA
ASIC
Verilog

Publications

Us Patents

Method And System For Predictive Mosfet Layout Generation With Reduced Design Cycle

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US Patent:
6728942, Apr 27, 2004
Filed:
Jun 12, 2001
Appl. No.:
09/879142
Inventors:
Koen Lampaert - Irvine CA
Andy Brotman - Irvine CA
Paolo Miliozzi - Newport Beach CA
Paramjit Singh - Lake Forest CA
Mishel Matloubian - Irvine CA
Bijan Bhattacharyya - Irvine CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
G06F 1750
US Classification:
716 10, 716 18, 716 8, 716 11, 716 12
Abstract:
In one disclosed embodiment, a number of parameter values for an RF MOSFET are received. Examples of parameter values are style, bulk contact, finger width, finger length, number of fingers, current, and slice parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the RF MOSFET are determined. For example, parasitic resistor values and parasitic capacitor values of the RF MOSFET are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the RF MOSFET. An RF MOSFET layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the RF MOSFET. As such, the parasitic values of the RF MOSFET have already been taken into account in the initial circuit simulation.

Method And System For Predictive Multi-Component Circuit Layout Generation With Reduced Design Cycle

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US Patent:
6839887, Jan 4, 2005
Filed:
Oct 24, 2001
Appl. No.:
10/029476
Inventors:
Andy Brotman - Irvine CA, US
Paolo Miliozzi - Irvine CA, US
Paramjit Singh - Lake Forest CA, US
Mishel Matloubian - Irvine CA, US
Bijan Bhattacharyya - Irvine CA, US
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
G06F 9455
G06F 1750
G06F 945
US Classification:
716 11, 703 14, 716 5, 716 10, 716 12
Abstract:
One embodiment discloses receiving a number of parameter values for a multi-component circuit. From the received parameter values, a number of parasitic values for various components in the multi-component circuit are determined. For example, parasitic resistor values and parasitic capacitor values for transistors in the multi-component circuit are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the multi-component circuit. According to a disclosed embodiment, a layout of the multi-component circuit is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the multi-component circuit. As such, the parasitic values of the multi-component circuit have already been taken into account in the initial circuit simulation and there is no need to extract the internal parasitics of the multi-component circuit for further circuit simulations.

Method And System For Predictive Layout Generation For Inductors With Reduced Design Cycle

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US Patent:
6588002, Jul 1, 2003
Filed:
Aug 28, 2001
Appl. No.:
09/941883
Inventors:
Koen Lampaert - Irvine CA
Andy Brotman - Irvine CA
Paolo Miliozzi - Irvine CA
Paramjit Singh - Lake Forest CA
Mishel Matloubian - Irvine CA
Bijan Bhattacharyya - Irvine CA
Francis M Rotella - Tustin CA
Rajesh Divecha - Irvine CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
G06F 1750
US Classification:
716 8, 716 12, 703 2, 703 16
Abstract:
In one embodiment, a number of parameter values for an inductor, such as a spiral inductor, are received. Examples of the parameter values are Number of Turns, Spacing, Width, Xsize, and Ysize parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the inductor are determined. For example, parasitic resistor values and parasitic capacitor values of the inductor are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the inductor. An inductor layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the inductor. As such, the parasitic values of the inductor have already been taken into account in the initial circuit simulation and, there is no need to extract the internal parasitics of the inductor for further circuit simulations.
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Bijan K Bhattacharyya from Irvine, CA, age ~73 Get Report