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Bhavana Bhoovaraghan Phones & Addresses

  • 2469 Louis Rd, Palo Alto, CA 94303
  • Lake Stevens, WA
  • Fremont, CA
  • East Lansing, MI
  • 823 Huntington Dr, Fishkill, NY 12524 (845) 896-1931
  • Sunnyvale, CA
  • White Plains, NY
  • Berkeley, CA
  • 1106 Starfish Ter, Fremont, CA 94536

Work

Company: Ibm Nov 2008 Position: Sram design engineer

Education

Degree: MS School / High School: Michigan State University 2001 to 2003 Specialities: Electrical Engineering

Skills

Semiconductors • Design of Experiments • Cross Functional Team Leadership • Manufacturing • Engineering Management • Characterization • Ic • Failure Analysis • Testing • Product Development • Six Sigma • Electronics • Spc • Process Engineering

Industries

Computer Software

Resumes

Resumes

Bhavana Bhoovaraghan Photo 1

Technical Program Manager Accounts Receivable And Vr

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Location:
2469 Louis Rd, Palo Alto, CA 94303
Industry:
Computer Software
Work:
IBM since Nov 2008
SRAM Design Engineer

IBM Dec 2005 - Nov 2008
Elec Characterization Engineer

Novellus Systems Jul 2004 - Nov 2005
Manufacturing Engineer
Education:
Michigan State University 2001 - 2003
MS, Electrical Engineering
KV
Skills:
Semiconductors
Design of Experiments
Cross Functional Team Leadership
Manufacturing
Engineering Management
Characterization
Ic
Failure Analysis
Testing
Product Development
Six Sigma
Electronics
Spc
Process Engineering

Publications

Us Patents

Leakage Measurement Of Through Silicon Vias

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US Patent:
20130069062, Mar 21, 2013
Filed:
Sep 15, 2011
Appl. No.:
13/233085
Inventors:
Bhavana Bhoovaraghan - Fishkill NY, US
Mukta G. Farooq - Hopewell Junction NY, US
Emily R. Kinser - Poughkeepsie NY, US
Sudesh Saroop - Poughkeepsie NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 23/58
H01L 21/66
US Classification:
257 48, 438 18, 257E21531, 257E23002
Abstract:
A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate having a plurality of through substrate vias for current leakage.
Bhavana Bhoovaraghan from Palo Alto, CA, age ~44 Get Report