Adam S Shepela

6678951, Jan 20, 2004

Dec 12, 2000

09/735566

Eugenia Atakov - Acton MA
Adam Shepela - Bolton MA
Lawrence Bair - Littleton MA
John Clement - Westboro MA
Bruce Gieseke - Ashland MA

Hewlett-Packard Development Company, L.P. - Houston TX

H05K 302

29847, 29852, 29DIG 16, 174250, 174255

A method is provided for forming an electrical conductors, comprising forming electrically conductive segments incorporating electromigration-inhibiting plugs. A row of windows is formed in a planar surface and electromigration-inhibiting material is deposited over the planar surface and into the windows to provide electromigration-inhibiting plugs in the windows. The plugs may be formed by depositing an electromigration-inhibiting liner in the windows and then depositing electrically conductive material to fill the windows. Portions of either or both of the plugs and conductive segments are removed such that the plugs and conductive segments have a coplanar surface. The plugs may be formed in windows in an electrically conductive layer defining the conductive segments. Alternatively, windows may be formed in a dielectric layer and the conductive segments formed from electrically conductive material deposited in trenches in the dielectric between neighboring windows, the plugs, conductive segments and dielectric surface being coplanar. Embodiments of the method may be employed in manufacture of integrated circuit conductors.

6904675, Jun 14, 2005

Oct 1, 2003

10/676443

Eugenia Atakov - Acton MA, US
Adam Shepela - Bolton MA, US
Lawrence Bair - Littleton MA, US
John Clement - Westboro MA, US
Bruce Gieseke - Ashland MA, US

Hewlett-Packard Development, L.P. - Houston TX

H01K003/10

29852, 29825, 29846, 438623, 438627, 438633, 438643, 438648, 438656, 438680, 438681, 438780, 438781

A method is provided for forming an electrical conductors, comprising forming electrically conductive segments incorporating electromigration-inhibiting plugs. A row of windows is formed in a planar surface and electromigration-inhibiting material is deposited over the planar surface and into the windows to provide, electromigration-inhibiting plugs in the windows. The plugs may be formed by depositing an electromigration-inhibiting liner in the windows and then depositing electrically conductive material to fill the windows. Portions of either or both of the plugs and conductive segments are removed such that the plugs and conductive segments have a coplanar surface. The plugs may be formed in windows in an electrically conductive layer defining the conductive segments. Alternatively, windows may be formed in a dielectric layer and the conductive segments formed from electrically conductive material deposited in trenches in the dielectric between neighboring windows, the plugs, conductive segments and dielectric surface being coplanar. Embodiments of the method may be employed in manufacture of integrated circuit conductors.

7062850, Jun 20, 2006

Oct 8, 2003

10/681843

Eugenia Atakov - Acton MA, US
Adam Shepela - Bolton MA, US
Lawrence Bair - Littleton MA, US
John Clement - Westboro MA, US
Bruce Gieseke - Ashland MA, US

Hewlett-Packard Development Company, L.P. - Houston TX

H05K 3/10
H01L 21/441
C23C 20/02

29852, 29846, 29831, 427 972, 427 977, 438675

A method of forming an electrical conductor, comprising forming electrically conductive segments incorporating electromigration-inhibiting plugs. A row of windows is formed in a planar surface and electromigraation-inhibiting material is deposited over the planar surface and into the windows to provide electromigration-inhibiting plugs in the windows. The plugs may be formed by depositing an electromigration-inhibiting liner in the windows and then depositing electrically conductive material to fill the windows. Portions of either or both of the plugs and conductive segments are removed such that the plugs and conductive segments have a coplanar surface. The plugs may be formed in windows in an electrically conductive layer defining the conductive segments. Embodiments of the method may be employed in manufacture of integrated circuit conductor.

62459961, Jun 12, 2001

May 20, 1999

9/316916

Eugenia Atakov - Acton MA
Adam Shepela - Bolton MA
Lawrence Bair - Littleton MA
John Clement - Westboro MA
Bruce Gieseke - Ashland MA

Compaq Computer Corporation - Houston TX

H01B 100
H05K 100

174 681

An integrated circuit is formed having electrical conductors with electromigration-inhibiting/electrically conductive plugs disposed between electrically conductive segments of the electrical conductor. Windows are formed within a planar surface. An electromigration-inhibiting/electrically conductive material is deposited over the planar surface and through the windows to fill the windows and thereby provide, in such windows, plugs of electromigration-inhibiting/electrically conductive material. Portions of the electromigration-inhibiting/electrically conductive material are removed to form the plugs with surfaces co-planar a surface surrounding the plugs. The electrical conductive segments are formed within the same planar surface as the plugs, either before, or after, the plug formation. The electrical conductive segments have surfaces co-planar with the plugs, are aligned with and electrically interconnected through the plugs. The plugs are formed at a distance less than, or equal to, the predetermined critical length, L. sub.

50949802, Mar 10, 1992

Sep 25, 1989

7/412634

Adam Shepela - Bolton MA

Digital Equipment Corporation - Maynard MA

H01L 2144

437189

By means of conventional deposition and lift-off processes, a metal contact plate is simultaneoulsy placed over transistor junction surfaces and over the surrounding field oxide boundary. After this process step, a dielectric layer, insulating the metal interconnect from the gate interconnect, is deposited and contact openings are plasma etched down to the metal contact plate, which acts to prevent erosion of the junction surface and the field oxide layer. When a diffusion barrier metal is used, the thermal stability of the contact resistance and the electromigration susceptibility are improved. While maintaining minimum transistor design dimensions and required alignment tolerances, the contacting metal plate allows for an increase in the contact opening area.

60603879, May 9, 2000

Nov 20, 1995

8/574557

Adam Shepela - Bolton MA
Gregory J. Grula - Charlton MA
Bjorn Zetterlund - Marlborough MA

Compaq Computer Corporation - Houston TX

H01L 214763

438630

A new process for creating a transistor in an integrated circuit provides for two suicide formations, each independent of the other, from two metal depositions and formations steps. The process produces a sufficiently low resistance silicide layer over the source/drain region surfaces of the transistor while also creating a lower resistance silicide over the gate interconnects. In an example embodiment of the invention a near-planar isolation process is used applied such that the gate interconnect surfaces are co-planar. A first silicide layer is formed over the source/drain regions. A dielectric gap-fill material is applied. A planarization method such as chemical mechanical polishing is used to remove the gap fill material down to the top surface of the gate interconnect. A relatively thick suicide is then formed over the top surface of the gate interconnect.