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Michael W Sheperek

from Berthoud, CO
Age ~64

Michael Sheperek Phones & Addresses

  • 1405 Linden St, Longmont, CO 80501
  • 430 Long View Ct, Longmont, CO 80501
  • 1509 Ithaca Ct, Longmont, CO 80503 (303) 651-1916
  • 3739 Fowler Ln, Longmont, CO 80503 (303) 651-1916
  • Berthoud, CO
  • Loveland, CO
  • Boulder, CO
  • Preston, WA
  • 1509 Ithaca Ct, Longmont, CO 80503

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: Bachelor's degree or higher

Professional Records

License Records

Michael W Sheperek

Address:
430 Long Vw Ct, Longmont, CO 80501
License #:
A5022410
Category:
Airmen

Publications

Us Patents

Temperature Compensation Systems And Methods For Use With Read/Write Heads In Magnetic Storage Devices

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US Patent:
7097110, Aug 29, 2006
Filed:
Dec 16, 2003
Appl. No.:
10/736661
Inventors:
Michael W. Sheperek - Longmont CO, US
Bryan E. Bloodworth - Irving TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
F24F 11/53
G01J 5/00
G01K 5/00
H01C 7/06
G11B 5/03
US Classification:
236 1C, 374132, 374185, 338 8, 338 9, 360 66
Abstract:
Disclosed herein are methods and systems for sensing and controlling the temperature of a resistive element configured for use in a read/write head of a magnetic data storage device. In one embodiment, a method includes detecting a voltage across the resistive element, where the voltage varies as a function of a temperature of the resistive element. The method also includes comparing the voltage to a predetermined value to determine a variation of the voltage from the predetermined value, and then altering a power applied to the resistive element based on the variation. In this exemplary embodiment, the temperature of the resistive element is then controlled as a function of the altered applied power.

Fly Height Control For A Read/Write Head In A Hard Disk Drive

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US Patent:
20050105204, May 19, 2005
Filed:
Nov 17, 2003
Appl. No.:
10/715217
Inventors:
Bryan Bloodworth - Irving TX, US
Congzhong Huang - Plano TX, US
Michael Sheperek - Longmont CO, US
Jeremy Kuehlwein - Woodbury MN, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11B021/02
US Classification:
360075000
Abstract:
A fly height controller (FHC; FHC′) for controlling the fly height of a read/write head assembly () in a disk drive () is disclosed. A heat element resistor () is disposed within the read/write head assembly (). The fly height controller (FHC; FHC′) includes registers (R, W) for storing digital data words corresponding to the desired drive levels to be applied to the heat element resistor () during read and write operations. The registers (R, W) are selectively coupled to a steady-state digital-to-analog converter (DAC) (), depending upon whether a read or write operation is occurring; the output of the steady-state DAC () is applied to a voltage driver (), which in turn drives current into the heat element resistor (). Overdrive and underdrive transistors (P, N) are provided to overdrive and underdrive the input to the voltage driver () in transitions between read and write operations. An initial state register () receives a digital word indicating the desired current for the heat element resistor () when unselected; the output of the initial state register () is applied to an initial state DAC (), which drives an initial state voltage driver (). Control logic (′) controls whether the steady-state voltage driver () or initial state voltage driver () drives the heat element resistor (). The fly height controller (FHC′) may also be adapted to control the fly height of multiple read/write head assemblies () in a disk drive.

Hidid Preamp-To-Host Interface With Much Reduced I/O Lines

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US Patent:
20060193071, Aug 31, 2006
Filed:
Feb 28, 2005
Appl. No.:
11/069031
Inventors:
Davy Choi - Garland TX, US
Michael Sheperek - Longmont CO, US
Bryan Bloodworth - Irving TX, US
Larry Koudele - Superior CO, US
International Classification:
G11B 5/09
G11B 5/02
US Classification:
360046000, 360067000
Abstract:
The present invention achieves technical advantages as a Preamp enabled to use different functional blocks inside the Preamp only during their own “active” modes. When a block is “inactive”, its corresponding I/O's are put into the High-impedance (Hi-Z) state so that all of the other “inactive” blocks do not affect operation of the one “active” block.

Generating Embedded Data In Memory Cells In A Memory Sub-System

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US Patent:
20220406381, Dec 22, 2022
Filed:
Aug 22, 2022
Appl. No.:
17/892721
Inventors:
- Boise ID, US
Michael Sheperek - Longmont CO, US
Larry J. Koudele - Erie CO, US
International Classification:
G11C 16/10
G11C 16/26
G06F 3/06
Abstract:
A processing device determines a target bit error rate corresponding to a point of a first programming voltage distribution level corresponding to memory cells of a memory sub-system and a second programming voltage distribution corresponding to the memory cells of the memory sub-system. An offset voltage level corresponding to the point at the target bit error rate is selected. A first portion of a first group of the memory cells in the first programming voltage distribution level is programmed at a threshold voltage level to set a first embedded data value. A second portion of a second group of the memory cells in the second programming voltage distribution level is programmed at the threshold voltage level offset by the offset voltage level to set a second embedded data value.

Smart Sampling For Block Family Scan

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US Patent:
20220366997, Nov 17, 2022
Filed:
Jul 29, 2022
Appl. No.:
17/877810
Inventors:
- Boise ID, US
Shane Nowell - Boise ID, US
Michael Sheperek - Longmont CO, US
Steven Michael Kientz - Westminster CO, US
International Classification:
G11C 29/44
G11C 29/42
G11C 29/12
G11C 29/10
G11C 16/34
Abstract:
A system can include a memory device and a processing device to perform operations that include determining a calibration scan frequency based on an amount of elapsed time since a previous write operation performed on the memory device, determining, based on the calibration scan frequency, whether one or more scan criteria are satisfied, responsive to determining that the one or more scan criteria are satisfied, identifying one or more block families, and calibrating one or more bin pointers of each of the identified block families, wherein the calibrating comprises: for each of the identified block families, updating each of the one or more bin pointers of the identified block family based on a data state metric of at least one block of the identified block family.

Dynamic Background Scan Optimization In A Memory Sub-System

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US Patent:
20220350538, Nov 3, 2022
Filed:
Jul 15, 2022
Appl. No.:
17/865686
Inventors:
- Boise ID, US
Michael Sheperek - Longmont CO, US
Francis Chew - Boulder CO, US
Bruce A. Liikanen - Berthoud CO, US
Larry J. Koudele - Erie CO, US
International Classification:
G06F 3/06
G06F 11/10
G11C 29/52
G06F 13/42
G06F 13/16
Abstract:
Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

Adjustment Of A Starting Voltage Corresponding To A Program Operation In A Memory Sub-System

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US Patent:
20220343981, Oct 27, 2022
Filed:
Jul 11, 2022
Appl. No.:
17/861467
Inventors:
- Boise ID, US
Michael Sheperek - Longmont CO, US
Larry J. Koudele - Erie CO, US
International Classification:
G11C 16/10
G06F 3/06
Abstract:
A processing device determines a measured bit error count (BEC) value corresponding to a read sample offset operation executed on a first programming voltage distribution of memory cells of a plurality of programming voltage distributions of a memory sub-system. The measured BEC value of the portion of the programming voltage distribution is compared to a threshold BEC value to generate a comparison result. In view of the comparison result, an adjusted program start voltage level is determined by adjusting a default program voltage level of a programming process. The programming process including a series of programming pulses is executed, where the adjusted program start voltage level is set as a starting voltage level of a first programming pulse of the series of programming pulses.

Error Avoidance Based On Voltage Distribution Parameters Of Blocks

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US Patent:
20220319589, Oct 6, 2022
Filed:
Mar 30, 2021
Appl. No.:
17/217772
Inventors:
- Boise ID, US
Steven Michael Kientz - Westminster CO, US
Michael Sheperek - Longmont CO, US
Mustafa N Kaynak - San Diego CA, US
Kishore Kumar Muchherla - San Jose CA, US
Larry J Koudele - Erie CO, US
Bruce A Liikanen - Berthoud CO, US
International Classification:
G11C 11/56
G11C 16/10
G11C 16/30
G11C 16/26
Abstract:
A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a data structure mapping block identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block of the memory device, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block, and reading, using the determined set of read levels, data from the block of the memory device.
Michael W Sheperek from Berthoud, CO, age ~64 Get Report