Search

Yuan Li

from San Jose, CA
Age ~61
Get Report
Related to:
Lan Li, 43Shuning LiYu LiKui Xu, 57Jell H LiAlice Liu, 69Yuanhai Li Hai, 57Zhaohong Li, 60Yuanhai Li, 58Li Kan Sum, 69Yuan Mli, 67Jingqiang Li, 51Hui Z Li, 54Gretchen L Law, 61Joan LiXue J Li, 57Kans Li
Connected to:
Ai Q Li, 64Ai H Li, 81Aida Li, 67Aijun Li, 65Aiwen Q Li, 56Aiyan Li, 61Alan Li, 80Alice Li, 46Alida Li, 59Alisha Li, 31

Yuan Li Phones & Addresses

  • San Jose, CA
  • Rowland Heights, CA

Professional Records

Lawyers & Attorneys

Yuan Li Photo 1

Yuan Li - Lawyer

View page
ISLN:
1000859236
Admitted:
2017

Medicine Doctors

Yuan Li Photo 2

Yuan Y. Li

View page
Specialties:
Internal Medicine
Work:
Castle Health Medical Office PC
3916 Prince St APT 5A, Flushing, NY 11354
(718) 358-6768 (phone), (718) 358-6783 (fax)
Education:
Medical School
Sun Yat Sen Univ of Med Sci, Guangzhou, China (242 21 Pr 1/71)
Graduated: 1987
Procedures:
Continuous EKG
Electrocardiogram (EKG or ECG)
Hearing Evaluation
Pulmonary Function Tests
Vaccine Administration
Conditions:
Abnormal Vaginal Bleeding
Acne
Acute Upper Respiratory Tract Infections
Alopecia Areata
Bacterial Pneumonia
Languages:
Chinese
English
Description:
Dr. Li graduated from the Sun Yat Sen Univ of Med Sci, Guangzhou, China (242 21 Pr 1/71) in 1987. She works in Flushing, NY and specializes in Internal Medicine. Dr. Li is affiliated with Flushing Hospital Medical Center and Queens Hospital Center.
Yuan Li Photo 3

Yuan Li, San Jose CA

View page
Specialties:
Acupuncture
Address:
1153 Johnson Ave, San Jose, CA 95129
(408) 725-2581 (Phone)
Languages:
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Yuan Li
Chief Executive
Fineworks Marble & Granite
Special Trade Contractors
1286 Purdue St, San Leandro, CA 94577
Yuan Li
Chief Executive
Fineworks Marble & Granite
Special Trade Contractors
1286 Purdue St, San Leandro, CA 94577
Yuan Li
Manager, Manager , Managing
TAYLOR TOWNHOMES LLC
Lessor of Multi-Family Housing · Multifamily Housing Rentals · Single-Family House Construction
3120 Springview Ln, Mount Hamilton, CA 95140
Yuan Li
U.S. Investment Regional Center, LLC
801 E Walnut St, Pasadena, CA 91101
Yuan Zheng Li
GOLDEN FLOWER INC
Yuan Li
CROSS TIME INTERNATIONAL TRADE LLC
Yuan W Li
JING & YINGS FOOD INC
Yuan Li
President
SUNRISE CAREGIVER FOUNDATION INC
Civic/Social Association
5670 Wilshire Blvd STE 1410, Los Angeles, CA 90036
388 E Vly Blvd, Alhambra, CA 91801
Yuan Ming Li
President
Jetta Tours & Bus Corporation
12711 Ramona Blvd, Duarte, CA 91706

Publications

Us Patents

Low Warpage Flip Chip Package Solution-Channel Heat Spreader

View page
US Patent:
6888238, May 3, 2005
Filed:
Jul 9, 2003
Appl. No.:
10/616858
Inventors:
Yuan Li - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L023/34
US Classification:
257706
Abstract:
A semiconductor package includes a chip carrier to receive a semiconductor with a dimension generally greater than 22 mm. The chip carrier has a first coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the semiconductor. A heat spreader having parallel channels on opposite sides is attached to the chip carrier along the channels. The heat spreader has a second coefficient of thermal expansion that is smaller than or equal to the coefficient of thermal expansion of the chip carrier. The interplay between the heat spreader and the chip carrier can effectively reduce package warpage and maintain coplanarity within the specification.

Structure And Material For Assembling A Low-K Si Die To Achieve A Low Warpage And Industrial Grade Reliability Flip Chip Package With Organic Substrate

View page
US Patent:
6909176, Jun 21, 2005
Filed:
Nov 20, 2003
Appl. No.:
10/719451
Inventors:
Wen-Chou Vincent Wang - Cupertino CA, US
Donald S. Fritz - San Jose CA, US
Yuan Li - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L023/10
US Classification:
257706, 257701, 257783, 257775
Abstract:
Provided are a semiconductor low-K Si die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the low-K Si die and packaging substrate. In general, the modulus of the thermal interface material, which is used to attach the heat spreader to the low-K Si die, is selected as high as possible relative to other commercially available thermal interface materials. On the other hand, the modulus of the adhesive, which is used to attach the heat spreader via an optional stiffener to the substrate, is selected as low as possible relative to other commercially available adhesives. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the low-K Si die and package reliabilities are thereby enhanced.

Flip Chip Package With Warpage Control

View page
US Patent:
6949404, Sep 27, 2005
Filed:
Nov 25, 2002
Appl. No.:
10/305671
Inventors:
Don Fritz - San Jose CA, US
Wen-chou Vincent Wang - Cupertino CA, US
Yuan Li - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L021/44
H01L021/48
H01L021/50
US Classification:
438106, 438107, 438108, 438125
Abstract:
Provided are a semiconductor flip chip package with warpage control and fabrication methods for such packages. The packages of the present invention include heat spreader lids that are rigidly attached to the die or packaging substrate with a bond that can withstand the considerable bowing pressures caused by the CTE mismatch between the die and substrate. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the PCB board to which it is ultimately bound. Package reliability is thereby also enhanced, particularly for large die sizes.

Low Stress And Warpage Laminate Flip Chip Bga Package

View page
US Patent:
7009307, Mar 7, 2006
Filed:
May 19, 2004
Appl. No.:
10/849651
Inventors:
Yuan Li - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L 23/48
H01L 23/52
H01L 29/40
US Classification:
257783, 257707, 438118
Abstract:
Provided are a semiconductor die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the die and packaging substrate. In general, the modulus of the adhesive, which is used to attach the heat spreader to the substrate, is selected to provide a relatively “soft” connection. The result is a package with less bowing and so improved co-planarity (e. g. , in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the die and package reliabilities are thereby enhanced.

Structure And Material For Assembling A Low-K Si Die To Achieve A Low Warpage And Industrial Grade Reliability Flip Chip Package With Organic Substrate

View page
US Patent:
7144756, Dec 5, 2006
Filed:
May 10, 2005
Appl. No.:
11/126571
Inventors:
Wen-Chou Vincent Wang - Cupertino CA, US
Donald S. Fritz - San Jose CA, US
Yuan Li - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01I 21/44
US Classification:
438106, 257E23001
Abstract:
Provided are a semiconductor low-K Si die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the low-K Si die and packaging substrate. In general, the modulus of the thermal interface material, which is used to attach the heat spreader to the low-K Si die, is selected as high as possible relative to other commercially available thermal interface materials. On the other hand, the modulus of the adhesive, which is used to attach the heat spreader via an optional stiffener to the substrate, is selected as low as possible relative to other commercially available adhesives. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the low-K Si die and package reliabilities are thereby enhanced.

Low Warpage Flip Chip Package Solution-Channel Heat Spreader

View page
US Patent:
7300822, Nov 27, 2007
Filed:
Apr 28, 2005
Appl. No.:
11/118630
Inventors:
Yuan Li - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L 21/00
US Classification:
438122, 257706
Abstract:
A semiconductor package includes a chip carrier to receive a semiconductor with a dimension generally greater than 22 mm. The chip carrier has a first coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the semiconductor. A heat spreader having parallel channels on opposite sides is attached to the chip carrier along the channels. The heat spreader has a second coefficient of thermal expansion that is smaller than or equal to the coefficient of thermal expansion of the chip carrier. The interplay between the heat spreader and the chip carrier can effectively reduce package warpage and maintain coplanarity within the specification.

Structure, Material, And Design For Assembling A Low-K Si Die To Achieve An Industrial Grade Reliability Wire Bonding Package

View page
US Patent:
7427813, Sep 23, 2008
Filed:
Nov 20, 2003
Appl. No.:
10/719218
Inventors:
Wen-chou Vincent Wang - Cupertino CA, US
Yuan Li - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L 29/40
H01L 23/28
H01L 23/29
US Classification:
257790, 257643, 257787, 257656, 257727, 257734
Abstract:
Provided are semiconductor low-K Si die wire bonding packages with package stress control and fabrication methods for such packages. The packages include molding interface material applied onto the low-K Si die. In general, the molding interface material is selectively applied onto the low-K Si die surface in order to minimize to safe levels the package stress experienced by the low-K Si die. Selective application includes defining various combinatorial patterns of coated and non-coated regions. In addition, selective application may also include a general application of molding interface material to create a stress buffer zone. The results are packages with less stress experienced by the low-K Si die and so improved reliability (in compliance with industry specifications).

Pad Structures To Improve Board-Level Reliability Of Solder-On-Pad Bga Structures

View page
US Patent:
7446399, Nov 4, 2008
Filed:
Aug 4, 2004
Appl. No.:
10/911088
Inventors:
Yuan Li - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L 23/48
H01L 23/02
H01L 21/00
US Classification:
257669, 257674, 257784, 438119, 438646, 438612
Abstract:
The present invention is directed to a new bonding pad structure having a rugged contact interface that makes it more difficult for a crack to grow from the peripheral edge of the bonding pad. The rugged contact interface also helps to accumulate more solder paste on the edge of the bonding pad, increase the thickness of the solder layer near the pad edge and prevent the pad edge from being oxidized and turning into a crack initiation point.

Isbn (Books And Publications)

The Expressionist Landscape

View page
Author

Yuan Li

ISBN #

0817438351

The Expressionist Landscape: A Master Photographer's Approach

View page
Author

Yuan Li

ISBN #

0817438343

Xin Wen Wu Bao Hu Fa Ji Shi Shi Tiao Li Wen Da

View page
Author

Yuan Li

ISBN #

7801821947

Control profile
Yuan Li from San Jose, CA, age ~61 Get Report