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Yu Jie Cai

from San Lorenzo, CA
Age ~45
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Also known as:
Yu J Cai, Yu Y Cai, Yujie J Cai, Jie Cai Xu, Yu J Cal, Xu Cai
Related to:
Chunxi YeHaoqi Yu, 31Feng YuJingping Cai, 74Yueying Peng, 52Yi Cai Yu, 46Feng Yu, 60Martin CaiGuohua Cai, 48
Connected to:
Anping Cai, 46Bao K Cai, 67Beibei Cai, 35Biaodong Cai, 62Caitlin Cai, 34Cecilia Y Cai, 35Changqing Cai, 58Chao Cai, 45Chunli Cai, 52Cristina Cai, 41

Yu Cai Phones & Addresses

  • San Lorenzo, CA
  • Tucson, AZ
  • Oakland, CA
  • Alameda, CA

Resumes

Resumes

Yu Cai Photo 1

Vice President, Ip

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Location:
4612 Vereda Mar Del Sol, San Diego, CA 92130
Industry:
Biotechnology
Work:
Polsinelli Shughart PC since Jun 2010
Attorney
Jennings, Strouss & Salmon Sep 2009 - Jul 2010
Attorney
Jennings, Strouss & Salmon May 2008 - Aug 2008
Summer intern
Squire, Sanders and Dempsey Jan 2008 - May 2008
Spring intern
The Biodesign Institute Center of Innovative Medicine in-house May 2007 - Aug 2007
Summer intern
Education:
Arizona State University College of Law 2006 - 2009
J.D., Law University of Arizona 2000 - 2006
Ph.D, Plant Sciences and Genetics Shanghai Jiao Tong University 1997 - 2000
M.S., Biochemistry and Molecular Biology Shanghai Jiao Tong University 1993 - 1997
B.S., Biochemical Engineer
Skills:
Intellectual Property
Patents
Licensing
Patent Prosecution
Legal Research
Trade Secrets
Trademarks
Litigation
Patent Litigation
Legal Writing
Patentability
Biotechnology
Invention
Corporate Law
Patent Law
Commercial Litigation
Life Sciences
Copyright Law
Trademark Infringement
Lifesciences
Registered Patent Attorney
Interests:
Classical Music
Ballroom Dancing
Spinning
Reading
Hiking
Languages:
English
Mandarin
Yu Cai Photo 2

Yu Cai

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Yu Cai Photo 3

Yu Cai

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Yu Cai Photo 4

Yu Cai

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Yu Cai Photo 5

Senior System Engineer At Huawei

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Position:
Senior Design Engineer/State Key Laboratory of Radio Access Technologies at Huawei
Location:
Shenzhen, Guangdong, China
Industry:
Wireless
Work:
Huawei - China since Mar 2012
Senior Design Engineer/State Key Laboratory of Radio Access Technologies
Bitswave Inc Jan 2011 - Mar 2012
DSP Hardware Engineer
Texas Instruments Aug 2010 - Dec 2010
Application Engineer
Halliburton Sep 2009 - Aug 2010
Senior Design Engineer
Subsurface sensing laboratory, University of Houston Jan 2006 - Jul 2009
Research Assistant/DSP Engineer
Education:
University of Houston 2006 - 2009
PhD, Electrical Engineering University of Cincinnati 2003 - 2006
Xi'an Jiaotong University 1999 - 2002
Master of Science; Bachelor of Science, Electrical Engineering Xi'an Jiaotong University 1995 - 1999
BS, EE
Yu Cai Photo 6

Yu Cai

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Location:
United States
Yu Cai Photo 7

Yu Cai

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Yu Cai
Global Network Solutions LLC
Computer Part Sales · Network Hardware Sale
580 California St, San Francisco, CA 94104
1549 Fieldcrest Dr, Concord, CA 94523
Yu Feng Cai
CONNECT INT'L NETWORK INC

Publications

Us Patents

Soft Chip-Kill Recovery For Multiple Wordlines Failure

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US Patent:
20200319970, Oct 8, 2020
Filed:
Jun 18, 2020
Appl. No.:
16/905787
Inventors:
- Gyeonggi-do, KR
Aman Bhatia - San Jose CA, US
Chenrong Xiong - San Jose CA, US
Yu Cai - San Jose CA, US
Fan Zhang - Fremont CA, US
International Classification:
G06F 11/10
G11C 29/52
H03M 13/37
H03M 13/45
H03M 13/11
H03M 13/13
H03M 13/29
Abstract:
Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.

Soft Chipkill Recovery For Bitline Failures

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US Patent:
20200210286, Jul 2, 2020
Filed:
Dec 17, 2019
Appl. No.:
16/717857
Inventors:
- Icheon-si, KR
Chenrong Xiong - San Jose CA, US
Aman Bhatia - San Jose CA, US
Yu Cai - San Jose CA, US
Fan Zhang - San Jose CA, US
International Classification:
G06F 11/10
H03M 13/11
H03M 13/45
Abstract:
Disclosed are devices, systems and methods for improving performance of a block of a memory device. In an example, performance is improved by implementing soft chipkill recovery to mitigate bitline failures in data storage devices. An exemplary method includes encoding each horizontal row of cells of a plurality of memory cells of a memory block to generate each of a plurality of codewords, and generating a plurality of parity symbols, each of the plurality of parity symbols based on diagonally positioned symbols spanning the plurality of codewords.

Storage Device Performance Optimization Using Deep Learning

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US Patent:
20200210831, Jul 2, 2020
Filed:
Dec 17, 2019
Appl. No.:
16/717888
Inventors:
- Icheon-si, KR
Yu Cai - San Jose CA, US
Chenrong Xiong - San Jose CA, US
Xuanxuan Lu - San Jose CA, US
International Classification:
G06N 3/08
G06N 3/04
Abstract:
Disclosed is a computer-implemented method for optimizing read thresholds of a memory device using a deep neural network engine, comprising reading, using a set of read threshold voltages applied to the memory device, data from the memory device under a first set of operating conditions that contribute to read errors in the memory device, producing a labeled training data set using the set of read threshold voltages under the first set of the operating conditions, determining, based on characteristics of the memory device, a number of layers, a size of each layer, and a number of input and output nodes of the deep neural network engine, training the deep neural network engine using the labeled training data set, and using the trained deep neural network engine to compute read thresholds voltage values under a second set of operating conditions.

Memory System And Method For Read Operation Based On Grouping Of Word Lines

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US Patent:
20200185040, Jun 11, 2020
Filed:
Dec 11, 2019
Appl. No.:
16/711003
Inventors:
- Gyeonggi-do, KR
Chenrong XIONG - San Jose CA, US
Fan ZHANG - Fremont CA, US
Naveen KUMAR - San Jose CA, US
Xuanxuan LU - San Jose CA, US
Yu CAI - San Jose CA, US
International Classification:
G11C 16/26
G11C 16/04
G11C 16/30
G11C 16/08
G06F 12/10
Abstract:
A memory system includes a memory device and a controller. The controller determines a target word line group to which a target word line corresponding to a read command belongs. The controller identifies a reference voltage corresponding to the target word line group. The controller controls the memory device to perform a read operation on a target page coupled to the target word line, using the reference voltage.

Memory System To Process Multiple Word Line Failures With Limited Storage And Method Of Operating Such Memory System

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US Patent:
20200090731, Mar 19, 2020
Filed:
Sep 18, 2019
Appl. No.:
16/575224
Inventors:
- San Jose CA, US
Yu CAI - San Jose CA, US
Fan ZHANG - San Jose CA, US
International Classification:
G11C 11/408
G11C 11/409
G11C 29/12
H03M 13/45
H03M 13/25
Abstract:
Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDDC) decoding of codewords of failed word lines is performed with the updated soft information.

Dynamic Neighbor And Bitline Assisted Correction For Nand Flash Storage

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US Patent:
20200042384, Feb 6, 2020
Filed:
May 23, 2019
Appl. No.:
16/421204
Inventors:
- Gyeonggi-do, KR
Aman Bhatia - San Jose CA, US
Yu Cai - San Jose CA, US
Fan Zhang - San Jose CA, US
International Classification:
G06F 11/10
G11C 29/52
H03M 13/45
Abstract:
A storage system includes memory cells arranged in an array and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to perform a read operation in response to a read command from a host, perform a first soft decoding of data from the read operation using existing LLR (log likelihood ratio) values stored in the memory controller, update existing LLR values using LLR values from neighboring memory cells and existing weight coefficients that account for influence from the neighboring memory cells. The memory controller is also configured to perform a second soft decoding using the updated LLR values. If the second soft decoding is successful, the memory controller performs a recursive update of weight coefficients to reflect updated influence from neighboring memory cells and stores the updated weight coefficient in the memory controller for use in further decoding.

Memory System And Method For Optimizing Read Threshold

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US Patent:
20200027519, Jan 23, 2020
Filed:
Jul 23, 2019
Appl. No.:
16/519445
Inventors:
- San Jose CA, US
Yu CAI - San Jose CA, US
Chenrong XIONG - San Jose CA, US
Xuanxuan LU - San Jose CA, US
International Classification:
G11C 29/38
G06F 3/06
Abstract:
A memory system includes a memory device and a controller. The controller performs a test read operation on a read data set of the memory device, using multiple read threshold entries and determines which are good read threshold entries based on results of the read operation. The controller selects a best read threshold entry among the multiple read threshold entries based on a result of the test read operation, partitions the read data set into a good data set decodable by the best read threshold entry and a bad data set undecodable by the best read threshold entry, and sets the bad data set as a new read data set.

Media Quality Aware Ecc Decoding Method Selection To Reduce Data Access Latency

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US Patent:
20200004626, Jan 2, 2020
Filed:
Sep 9, 2019
Appl. No.:
16/565120
Inventors:
- Gyeonggi-do, KR
Fan ZHANG - Fremont CA, US
Yu CAI - San Jose CA, US
International Classification:
G06F 11/10
Abstract:
A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.
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Yu Jie Cai from San Lorenzo, CA, age ~45 Get Report