Hao Q Yu

7639059, Dec 29, 2009

Sep 12, 2007

11/853827

Hao Yu - Fremont CA, US
Sing Chin - Alameda CA, US
Bill Wong - Milpitas CA, US

National Semiconductor Corporation - Santa Clara CA

H03L 5/00

327333, 327108, 326 81, 365226

A reference voltage buffer circuit () includes first and second transistors (M, M) and first and second resistors (R, R) connected in series between positive and negative power supply voltages and providing a positive reference voltage (Vrp) and a negative reference voltage (Vrn) at the first current handling terminals of the first and second transistors, respectively. A first control voltage (Vg) for driving the first transistor is generated by a first feedback loop and using a positive boosted voltage. A second control voltage (Vg) for driving the second transistor is generated by a second feedback loop and using a negative boosted voltage. The first and second feedback loops establish the first and second control voltages while the positive and negative boosted voltages ensure sufficient drives are provided to the first and second transistors. The reference voltage buffer is capable of fast settling while maintaining a wide reference voltage range.

7705649, Apr 27, 2010

Apr 3, 2008

12/062426

Hao Yu - Fremont CA, US
Sing W. Chin - Alameda CA, US
Bill C. Wong - Milpitas CA, US

National Semiconductor Corporation - Santa Clara CA

H03K 3/017

327175, 327158

A duty cycle correction circuit () for receiving an input clock signal () and generating an output clock signal () having a predetermined duty cycle includes a clock trigger circuit () generating the output clock signal () having a first clock edge triggered from the input clock signal and a second clock edge triggered from a delayed clock signal (); a charge pump circuit () receiving the output clock signal and generating charging and discharging currents for a capacitor (C) where a control voltage develops on the capacitor indicative of the duty cycle error of the output clock signal; a self-track bias circuit () receiving the control voltage and generating first and second bias voltages () in response to the control voltage; and a delay-locked loop circuit () receiving the output clock signal and the first and second bias voltages and generating the delayed clock signal.

7267940, Sep 11, 2007

Mar 4, 2003

10/382085

Peilin Chen - Cupertino CA, US
Peter Su - Mercer Island WA, US
Hao Yu - Pacheco CA, US
Lawrence J. Blecka - Walnut Creek CA, US
Patrick F. Coleman - Edmonds WA, US

Bio-Rad Laboratories, Inc. - Hercules CA

A61K 39/245
C07K 14/035
G01N 33/543
G01N 33/546
G01N 33/53
C12Q 1/70

435 5, 530324, 435 71, 436518, 436533

The present invention relates to peptides that are derived from HSV-2 glycoprotein G2 and represent HSV-2 type-specific epitopes. The present invention also provides for compositions comprising these peptides for type-specific serological diagnosis of HSV-2 infection. Methods of using these peptides for type-specific detection of HSV-2 antibodies and differentiation of HSV-2 viral infection from HSV-1 and other herpes family viral infections are further provided.

20050048468, Mar 3, 2005

Aug 27, 2003

10/650595

Peilin Chen - Cupertino CA, US
Hao Yu - Pacheco CA, US
Lawrence Blecka - Walnut Creek CA, US
Steve Binder - Berkeley CA, US

Bio-Rad Laboratories, Inc. - Hercules CA

C12Q001/70
A61K039/42

435005000, 424159100

A serum in which are dissolved at least two heterologous antibodies, which are independently IgG or IgM and which specifically bind to different antigens, serves as a calibrator for multi-analyte immunoassays.