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Yinghua Li

from San Jose, CA
Age ~45
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Also known as:
Li Yinghua, Liying Hua
Phone and address:
2199 Ashwood Ln, San Jose, CA 95132
(770) 624-1914
Related to:
Li Li, 36Longchain Chen, 86Limin Xiao, 39Qin Li, 57Nan Xiao, 44Li YinghuaLi Zhen, 39Ding B Li, 56Li C HsuJian Li, 49Zhenguang Xiao
Connected to:
Ai Q Li, 64Ai H Li, 81Aida Li, 67Aijun Li, 65Aiwen Q Li, 56Aiyan Li, 61Alan Li, 80Alice Li, 46Alida Li, 59Alisha Li, 31

Yinghua Li Phones & Addresses

  • 2199 Ashwood Ln, San Jose, CA 95132 (770) 624-1914
  • Milpitas, CA
  • Duluth, GA
  • Suwanee, GA
  • Greenville, NC
  • Santa Clara, CA
  • Asheville, NC

Resumes

Resumes

Yinghua Li Photo 1

Software Engineer

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Location:
San Francisco, CA
Industry:
Internet
Work:
Facebook
Software Engineer
Cadence Design Systems 2012 - 2015
Senior Member of Consulting Staff
Yahoo 2012 - 2015
Senior Software Engineer
Cadence Design Systems Jan 1, 2009 - 2012
Member of Consulting Staff
Magma Fincorp Ltd. Oct 2005 - Mar 2009
Senior Member of Technical Staff
Education:
University of California, Berkeley 2000 - 2005
Doctorates, Doctor of Philosophy, Electrical Engineering Peking University 1996 - 2000
Bachelors, Bachelor of Science, Electrical Engineering University of California
Certifications:
Machine Learning
Coursera
Yinghua Li Photo 2

General Dentist

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Work:
Mds
General Dentist
Yinghua Li Photo 3

Yinghua Li

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Yinghua Li Photo 4

Yinghua Li

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Yinghua Li Photo 5

Yinghua Li

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Yinghua Li
GREENMAX TECHNOLOGIES INC
Yinghua Li
YINGHUA LI FAMILY LIMITED PARTNERSHIP
Yinghua Li
EXCEL TECH & TRADING COMPANY LIMITED
Yinghua Li
YINGHONG FAMILY LIMITED PARTNERSHIP
Yinghua Li
HONGXU SU FAMILY LIMITED PARTNERSHIP
Yinghua Li
HUAXU FAMILY LIMITED PARTNERSHIP

Publications

Us Patents

Method For Optimized Automatic Clock Gating

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US Patent:
7882461, Feb 1, 2011
Filed:
May 28, 2008
Appl. No.:
12/128574
Inventors:
Yunjian (William) Jiang - San Jose CA, US
Arvind Srinivasan - San Jose CA, US
Joy Banerjee - District Burdwan, IN
Yinghua Li - San Jose CA, US
Partha Das - Kolkata, IN
Samit Chaudhuri - Cupertino CA, US
Assignee:
Magma Design Automation, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 2, 716 4, 327175, 323284, 702 63
Abstract:
A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

Method For Automatic Clock Gating To Save Power

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US Patent:
7930673, Apr 19, 2011
Filed:
May 28, 2008
Appl. No.:
12/128554
Inventors:
Yunjian (William) Jiang - San Jose CA, US
Arvind Srinivasan - San Jose CA, US
Joy Banerjee - District Burdwan, IN
Yinghua Li - San Jose CA, US
Partha Das - Kolkata, IN
Samit Chaudhuri - Cupertino CA, US
Assignee:
Magma Design Automation, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716132, 716119, 716136, 713500
Abstract:
A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.

Multi-Level Clock Gating Circuitry Transformation

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US Patent:
8434047, Apr 30, 2013
Filed:
Jan 25, 2011
Appl. No.:
13/013024
Inventors:
Yunjian (William) Jiang - San Jose CA, US
Arvind Srinivasan - San Jose CA, US
Joy Banerjee - District Burdwan, IN
Yinghua Li - San Jose CA, US
Partha Das - Kolkata, IN
Samit Chaudhuri - Cupertino CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716133, 716109, 716132
Abstract:
A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

Crosstalk-Aware Timing Analysis

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US Patent:
20060080627, Apr 13, 2006
Filed:
Jul 8, 2005
Appl. No.:
11/178111
Inventors:
Rajeev Murgai - Santa Clara CA, US
Yinghua Li - Albany CA, US
Takashi Miyoshi - San Jose CA, US
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716006000
Abstract:
In one embodiment, a method for crosstalk-aware timing analysis includes accessing a design of a circuit and identifying critical paths in the design. Each critical path includes one or more victim interconnects and one or more cells. The method includes identifying potential aggressor interconnects associated with each victim interconnect and, for each victim interconnect, extracting parasitics of the victim interconnect and the potential aggressor interconnects associated with the victim interconnect. The method includes computing timing windows of the potential aggressor interconnects and computing a first timing of each cell and each victim interconnect on each critical path. The method also includes, for each critical path, generating timing waveforms of the potential aggressor interconnects, traversing the critical path from a start point on the critical path to an end point on the critical path, and, computing a second timing of each cell and each victim interconnect on the critical path according to a traversal of the critical path.
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Yinghua Li from San Jose, CA, age ~45 Get Report