Yi Li D He

6436768, Aug 20, 2002

Jun 27, 2001

09/893279

Jean Yee-Mei Yang - Sunnyvale CA
Mark T. Ramsbey - Sunnyvale CA
Emmanuil Manos Lingunis - San Jose CA
Yider Wu - San Jose CA
Tazrien Kamal - San Jose CA
Yi He - Sunnyvale CA
Edward Hsia - Saratoga CA
Hidehiko Shiraiwa - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited

H01L 21336

438266, 438257

One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.

6639844, Oct 28, 2003

Mar 13, 2002

10/099499

Zhizheng Liu - Sunnyvale CA
Yi He - Sunnyvale CA
Mark W. Randolph - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G11C 1604

3651853, 36518522, 36518529, 36518533

A method for correcting overerasure in a multi-bit memory device. A sector of multi-bite memory cells in the device is erased and verified. After erase and verification, the overerased memory cells are soft programmed and verified to correct for overerasure. A soft programming pulse with a V to V ratio (V /V ) greater than or equal to two is used.

6697561, Feb 24, 2004

Feb 15, 2002

10/078197

Yi He - Saratoga CA

Global Option, Inc. - Santa Clara CA

G02B 0600

385140

A Variable Optical Attenuation Collimator (VOAC) is disclosed to achieve a variable degree of optical power attenuation through the collimator by adding an Attenuation Control Element (ACE) between a lens element and fiber pigtails of a traditional fiber optical collimator. The body of the ACE can be implemented in many different ways such as a polymer-network liquid crystal light scattering and absorbing material, a Refraction Index Gradient Controllable Material (RIGCM) capable of controllably swerving the direction of light propagation, a Refraction Index Controllable Material (RICM) capable of controllably defocusing an incident light power and a transparent Length Controllable Material (LCM) capable of controllably changing the spacing between the lens element and the fiber pigtails causing a defocusing of an incident light power.

6707981, Mar 16, 2004

Feb 15, 2002

10/078219

Yi He - Saratoga CA

Global Opticom, Inc. - Santa Clara CA

G02B 600

385140, 385 34, 385 73

A concept of designing a Variable Optical Attenuation Collimator (VOAC) is disclosed to achieve a variable degree of optical power attenuation through the collimator by adding an Attenuation Control Element (ACE) between a lens element and fiber pigtails of a traditional fiber optical collimator. The body of the ACE can be implemented in many different forms of a light blocker element capable of being controllably moved into a main light path of the VOAC to obstruct a controlled portion of light power. The light blocker can be a Micro Electro Mechanical Structure (MEMS) operating with a controlled electrostatic force, a bimetal wire driven by a controlled heating current, an electrical current-carrying wire within a surrounding permanent magnetic field or a deflectable permanent magnetic wire within a controlled surrounding magnetic field.

6768673, Jul 27, 2004

Apr 24, 2003

10/422276

Edward Hsia - Saratoga CA
Darlene Hamilton - San Jose CA
Kulachet Tanpairoj - Palo Alto CA
Mimi Lee - Santa Clara CA
Alykhan F. Madhani - Santa Clara CA
Yi He - Fremont CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G11C 1604

36518503, 36518524

A method of programming and reading a dual cell memory device. The method includes storing a selected program level in each cell and reading one of the cells to determine a single data value stored by the memory device.

6771545, Aug 3, 2004

Jan 29, 2003

10/353558

Edward Hsia - Saratoga CA
Eric Ajimine - Saratoga CA
Darlene G. Hamilton - San Jose CA
Pauling Chen - Saratoga CA
Ming-Huei Shieh - Cupertino CA
Mark W. Randolph - San Jose CA
Edward Runnion - Santa Clara CA
Yi He - Fremont CA

Advanced Micro Devices Inc. - Sunnyvale CA

G11C 1604

36518529, 3651853, 36518511

An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a charge within a selected plurality of the memory cells within the active column. The selected plurality of memory cells represents a portion of the data pattern. An inactive memory cell programming pattern is identified. The inactive memory cell programming pattern identifies all, or a selected plurality, of the memory cells in the inactive column in which a charge is to be stored for the purpose of periodically storing a charge in the memory cells first inactive column to prevent over erasure, during bulk erase, and leakage from the inactive cells to adjacent active cells. A charge is stored on the selected plurality of the memory cells in the first inactive column. The data pattern is reproduced reading each memory cell within the first active column.

6788583, Sep 7, 2004

Dec 2, 2002

10/307749

Yi He - Fremont CA
Edward F. Runnion - Santa Clara CA
Zhizheng Liu - Sunnyvale CA
Mark W. Randolph - San Jose CA
Darlene G. Hamilton - San Jose CA
Pauling Chen - Saratoga CA
Binh Le - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G11C 1606

36518525, 36518502, 36518521, 365203

A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

6795342, Sep 21, 2004

Dec 2, 2002

10/307667

Yi He - Fremont CA
Zhizheng Liu - Sunnyvale CA
Mark W. Randolph - San Jose CA
Sameer S. Haddad - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G11C 1604

36518516, 36518518

A system for programming a charge stored on a charge storage region of a dielectric charge trapping layer of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a positive source programming bias to a first bit line that is the source of the selected memory cell while applying a drain programming voltage to a second bit line that forms a drain junction with the channel region and while applying a positive voltage to a selected word line. The source voltage may be applied by coupling the source bit line to a voltage divider or by coupling the source bit line to a resistor which in turn is coupled to a ground. A negative programming bias may also be applied to the substrate and to unselected word lines.