Professional Records
License Records
Wen Li
License #:
4001009466
Category:
Real Estate Appraiser License
Wen Li Phones & Addresses
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2427 E Gloucester St, Boise, ID 83706
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Irving, TX
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Coppell, TX
Work
Position:
Professional/Technical
Education
Degree:
High school graduate or higher
Publications
Isbn (Books And Publications)
Vocational Education and Social Inequality in the United States
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Author
Wen Lang Li
ISBN #
0819118575
Vocational Education and Social Inequality in the United States
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Author
Wen Lang Li
ISBN #
0819118583
The Measurement and Analysis of Internal Migration Testing Models with Korean Data
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Author
Wen Lang Li
ISBN #
0819132187
The Measurement and Analysis of Internal Migration Testing Models with Korean Data
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Author
Wen Lang Li
ISBN #
0819132195
Determination of Dumping under GATT and EC Antidumping Regimes
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Author
Wen Xi Li
ISBN #
9154422213
Us Patents
Output Circuit For A Double Data Rate Dynamic Random Access Memory, Double Data Rate Dynamic Random Access Memory, Method Of Clocking Data Out From A Double Data Rate Dynamic Random Access Memory And Method Of Providing A Data Strobe Signal
View pageUS Patent:
6381194, Apr 30, 2002
Filed:
Apr 20, 2001
Appl. No.:
09/838861
Inventors:
Wen Li - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 800
US Classification:
365233, 36518902, 36523002
Abstract:
A method and apparatus for synchronizing output data and data strobe signals uses internal interleaved clock signals in a double data rate (DDR) DRAM that are synchronized with an external clock. A delay-locked loop internal to the DDR DRAM is locked to an external clock signal and generates the internal interleaved clock signals. The internal interleaved clock signals are delay matched with the external clock signal as they propagate through timing circuitry coupled to latency and burst length selection signals. A data strobe signal is generated using clock signals from the delay-locked loop and is synchronized with the internal interleaved clock signals. The data strobe signal and the data are coupled via paths having comparable numbers and types of delay elements to provide output data and data strobe signals having predetermined delay relationships with the external clock signal.
Method Of Reducing Standby Current During Power Down Mode
View pageUS Patent:
6438060, Aug 20, 2002
Filed:
Feb 12, 2001
Appl. No.:
09/780606
Inventors:
Wen Li - Boise ID
Mark R. Thomann - Boise ID
Daniel R. Loughmiller - Boise ID
Scott Schaefer - Boise ID
Mark R. Thomann - Boise ID
Daniel R. Loughmiller - Boise ID
Scott Schaefer - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365227, 36518905, 36523008, 365233
Abstract:
An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.
Memory Device With Synchronized Output Path
View pageUS Patent:
6446180, Sep 3, 2002
Filed:
Jul 30, 2001
Appl. No.:
09/918276
Inventors:
Wen Li - Boise ID
Christopher K. Morzano - Boise ID
Christopher K. Morzano - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 1200
US Classification:
711167, 713401, 713600, 365194, 365233, 327147, 327156
Abstract:
A memory device includes a data array, array control logic, a delay locked loop circuit, timing control logic, and a first storage device. The array control logic is adapted to receive a read command synchronized with an external clock signal and to read at least a first data element from the data array based on the read command. The delay locked loop circuit is adapted to receive the external clock signal and delay the external clock signal by a programmable amount to generate a delay locked loop clock signal. The timing control logic is adapted to generate a first input enable signal based on the external clock signal and a first output enable signal based on the delay locked loop clock signal. The first storage device adapted to receive the first data element. The first storage device has an input terminal enabled in response to the first input enable signal and an output terminal enabled in response to the first output enable signal.
Shared Redundancy For Memory Having Column Addressing
View pageUS Patent:
6480429, Nov 12, 2002
Filed:
Feb 12, 2001
Appl. No.:
09/781808
Inventors:
William F. Jones - Boise ID
Wen Li - Boise ID
Wen Li - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365200, 365233, 365235
Abstract:
A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory arrays, fuses may be used to provide access to the redundant columns. Because burst addressing may begin with a RIGHT segment address, two different columns may be accessed on the same clock cycle. By providing a compare scheme which implements separate compare logic for the lower bits of the LEFT and RIGHT segments and compares these bits to a common fuse set used for both the LEFT and RIGHT segments, the number of fuses in the redundant DDR SDRAM scheme can be reduced.
Write Data Masking For Higher Speed Drams
View pageUS Patent:
6532180, Mar 11, 2003
Filed:
Jun 20, 2001
Appl. No.:
09/883957
Inventors:
Kevin J. Ryan - Eagle ID
Christopher K. Morzano - Boise ID
Wen Li - Boise ID
Christopher K. Morzano - Boise ID
Wen Li - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365195, 36523003, 365233
Abstract:
A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is pre-empted, thereby masking data to be written to a memory device. By pre-empting the column selects, the margin required for disabling a write driver can be eliminated, thereby reducing the effective write cycle. Additionally, data masking can be performed on a per-byte basis by associating independent column selects with each data byte on multi-byte wide devices, e. g. , Ã16 or Ã32.
High Frequency Range Four Bit Prefetch Output Data Path
View pageUS Patent:
6556494, Apr 29, 2003
Filed:
Mar 14, 2001
Appl. No.:
09/808506
Inventors:
Christopher K. Morzano - Boise ID
Wen Li - Boise ID
Wen Li - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365219, 36518905, 365233
Abstract:
A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.
High Frequency Range Four Bit Prefetch Output Data Path
View pageUS Patent:
6600691, Jul 29, 2003
Filed:
Jul 29, 2002
Appl. No.:
10/207641
Inventors:
Christopher K. Morzano - Boise ID
Wen Li - Boise ID
Wen Li - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365219, 365221, 36518905, 365233
Abstract:
A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.
Cmos Output Driver For Semiconductor Device And Related Method For Improving Latch-Up Immunity In A Cmos Output Driver
View pageUS Patent:
6624660, Sep 23, 2003
Filed:
Dec 6, 2001
Appl. No.:
10/010820
Inventors:
Wen Li - Boise ID
Michael D. Chaine - Boise ID
Manny Kin Ma - Boise ID
Michael D. Chaine - Boise ID
Manny Kin Ma - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H03K 19094
US Classification:
326 83, 326 86, 327534
Abstract:
An output driver circuit for a semiconductor device. In one embodiment, the output driver is coupled to an output terminal of the semiconductor device and consists of an N-channel pull-down transistor and a P-channel pull-up transistor formed in an N-well in a P-type substrate. A tie-down region formed in the N-well is selectively coupled to a supply potential by means of a decoupling transistor, and during normal operation of the driver maintains the supply voltage bias of the N-well. An overdrive detection circuit is coupled to the output terminal. Upon detection of an overdrive condition on the output terminal, such as a voltage exceeding a predetermined maximum, or excessive current injected into the output terminal (or both), the overdrive detection circuit deasserts a control signal applied to the gate of the decoupling transistor, thereby decoupling the N-well from the supply potential. In one embodiment, the decoupling transistor is not coupled to the output terminal.