Wei Li

6591407, Jul 8, 2003

Mar 1, 2000

09/516489

Douglas Kaufman - Menlo Park CA
Hazem Almusa - San Jose CA
Vinay Srinivas - Redwood City CA
Donald V. Organ - Saratoga CA
Larry Ke - San Jose CA
Wei Li - Milpitas CA
Japinder Singh - Santa Clara CA
Robert Mathews - Los Altos CA

Sequence Design, Inc. - Santa Clara CA

G06F 1750

716 10, 716 2, 716 3, 716 9

A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, âhot spotsâ in the physical design are identified for local transformation using a âbidirectional combinational total negative slackâ (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

6721943, Apr 13, 2004

Mar 30, 2001

09/822736

Rakesh Krishnaiyer - Santa Clara CA
Somnath Ghosh - San Jose CA
Wei Li - Redwood City CA

Intel Corporation - Santa Clara CA

G06F 945

717150, 717140, 717151, 717158, 717160, 711105, 711111, 711114

In general, the malloc-combining transformation optimization during compile-time of a source program engaged in dynamically constructing multi-dimensional arrays provides an effective method of improving cache locality by combining qualified malloc and free/realloc calls found in counted loops into a single system call and hoisting out the single call and placing it immediately preceding the beginning of the counted loops. As a result of the application of the malloc-combining optimization results in improved cache locality allows for prefetching array pointers and data elements of the dynamic arrays as if the dynamic arrays were static.

6995794, Feb 7, 2006

May 18, 2001

09/861279

Mark Hsu - Fremont CA, US
Mitchell Norcross - Harvard MA, US
Georges Auberger - Emerald Hills CA, US
Remy Zimmermann - Belmont CA, US
Sergio Maggi - San Mateo CA, US
George Sanchez - Fremont CA, US
Bryed Billerbeck - Mountain View CA, US
Wei Li - Cupertino CA, US
Jean-Michel Junien Labrousse - Belmont CA, US

Logitech Europe S.A. - Romanel-sur-Morges

H04N 5/217
H04N 9/64

348241, 348243

A low cost camera by implementing the major functions in host software is provided. This is accomplished by sending raw, digitized data from the camera directly to the host. The increased volume of raw data is handled by either an improved compression/decompression scheme using lossless compression, using lossy compression or using a shared bus with higher bandwidth. By moving such functions as color processing and scaling to the host, the pixel correction can also be moved to the host. This in turn allows the elimination of the frame buffer memory from the camera. Finally, the camera can use a low cost lens by implementing vignetting, distortion, gamma or aliasing correction with a correction value stored in a register of the camera for later access by the host to perform corrections.

7155446, Dec 26, 2006

Jun 14, 2004

10/867923

Thierry Cruanes - Redwood City CA, US
Wei Li - San Carlos CA, US
Ari Mozes - Lexington MA, US
Benoit Dageville - Foster City CA, US

Oracle International Corporation - Redwood Shores CA

G06F 17/00

707101, 708320, 712 1

A method and apparatus for performing recursive database operations is provided. According to one aspect, a plurality of first-stage slaves and a plurality of second-stage slaves are established in a database server. During one or more iterations of a recursive database operation, the first-stage slaves concurrently process data items stored in a data repository and send results to the second-stage slaves. The second-stage slaves receive the results and concurrently process those results. The second-stage slaves store the results of the second-stage slaves' processing in the data repository. Subsequent iterations of the recursive database operation proceed in this manner until the recursive database operation has been completed. In each iteration, the first-stage slaves consume the product of the second-stage slaves' previous iteration's processing, and the second-stage slaves consume the product of the first-stage slaves' current iteration's processing.

7155575, Dec 26, 2006

Dec 18, 2002

10/323226

Rakesh Krishnaiyer - Santa Clara CA, US
Wei Li - Redwood City CA, US

Intel Corporation - Santa Clara CA

G06F 12/08

711137, 711169, 712207

A computer program product determines whether a loop has a high usage count. If the computer program product determines the loop has a high usage count, the computer program product determines whether the loop has an irregularly accessed load. If the loop has an irregularly accessed load, the computer program product inserts pattern recognition code to calculate whether successive iterations of the irregular memory load in the loop have a predictable access pattern. The computer program product implants conditional adaptive prefetch code including a prefetch instruction into the output code.

7157509, Jan 2, 2007

Jun 27, 2003

10/607111

Wei Helen Li - San Ramon CA, US
Stanley L. Lehmann - Martinez CA, US
Raymond S. Wong - San Ramon CA, US

Henkel Corporation - Rocky Hill CT

C08K 5/357

524 87, 528 94, 528403

Curable compositions, such as benzoxazine-based ones, are useful in applications within the aerospace industry, such as for example as a heat curable composition for use as a matrix resin or an adhesive, and form the basis of the present invention.

7222311, May 22, 2007

Mar 12, 2003

10/387644

Douglas Kaufman - Menlo Park CA, US
Hazem Almusa - San Jose CA, US
Vinay Srinivas - Redwood City CA, US
Donald V. Organ - Saratoga CA, US
Larry Ke - San Jose CA, US
Wei Li - Milpitas CA, US
Japinder Singh - Santa Clara CA, US
Robert Mathews - Los Altos CA, US

Sequence Design, Inc. - Santa Clara CA

G06F 17/50

716 2

A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

7228528, Jun 5, 2007

Jun 26, 2003

10/609246

Hong Wang - Fremont CA, US
Marsha Eng - Santa Clara CA, US
Perry Wang - San Jose CA, US
John P. Shen - San Jose CA, US
Gerolf F. Hoflehner - Santa Clara CA, US
Daniel Lavery - Santa Clara CA, US
Wei Li - Redwood City CA, US

Intel Corporation - Santa Clara CA

G06F 9/45
G06F 15/00

717131, 717153, 717154, 712231, 712233

In one embodiment, the invention provides a method for the processing of instructions. A method which comprises analyzing a dynamic execution trace for a program; identifying at least one stream comprising a plurality of basic blocks in the dynamic execution trace; collecting metrics associated with the at least one stream; and optimizing the at least one stream based on the metrics.