Wei Yu Li

6353691, Mar 5, 2002

Jan 27, 2000

09/492966

Wei Zhong Li - San Jose CA
Yanfeng Yang - Sunnyvale CA

Oplink Communications, Inc. - San Jose CA

G02B 600

385 11, 385 34, 359495

A method and system for providing a splitter/combiner is disclosed. The splitter/combiner includes a first birefringent wedge having a first optic axis and a first wedge angle and a second birefringent wedge having a second optic axis and a second wedge angle. The second birefringent wedge is optically coupled with the first birefringent wedge. The second wedge angle is complementary to the first wedge angle. The second optic axis is perpendicular to the first optic axis such that an extraordinary signal for the first birefringent wedge is an ordinary signal for the second birefringent wedge. The first and second birefringent wedges establish a first path for a first portion of a first optical signal and establish a second path for a second portion of the first optical signal. The first path and the second path are separated by an angle. The first optical signal travels from the first birefringent wedge to the second birefringent wedge.

6580828, Jun 17, 2003

Jun 30, 1999

09/343934

Wei Li - Cupertino CA

Logitech Europe, S.A. - Romanel-sur-Morges

G06K 936

382233, 382246, 708203, 341 67

New and improved variable length decoding methods and apparatus. The present invention provides speed performance and efficiency for decoding data by comparing, in parallel, a first plurality of code words of received data with respective values from a code length table. If the compared first plurality of code words are outside of a criterion, a second plurality of code words of received data are compared with respective values from the code length table. If one of the code words from one of the first and the second compared plurality of code words meets the criterion, it is determined which one of the code words from the first and the second compared plurality of code words has met the criterion. Once the code word meeting the criterion is determined, its symbol value is provided.

6591407, Jul 8, 2003

Mar 1, 2000

09/516489

Douglas Kaufman - Menlo Park CA
Hazem Almusa - San Jose CA
Vinay Srinivas - Redwood City CA
Donald V. Organ - Saratoga CA
Larry Ke - San Jose CA
Wei Li - Milpitas CA
Japinder Singh - Santa Clara CA
Robert Mathews - Los Altos CA

Sequence Design, Inc. - Santa Clara CA

G06F 1750

716 10, 716 2, 716 3, 716 9

A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, âhot spotsâ in the physical design are identified for local transformation using a âbidirectional combinational total negative slackâ (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

6721943, Apr 13, 2004

Mar 30, 2001

09/822736

Rakesh Krishnaiyer - Santa Clara CA
Somnath Ghosh - San Jose CA
Wei Li - Redwood City CA

Intel Corporation - Santa Clara CA

G06F 945

717150, 717140, 717151, 717158, 717160, 711105, 711111, 711114

In general, the malloc-combining transformation optimization during compile-time of a source program engaged in dynamically constructing multi-dimensional arrays provides an effective method of improving cache locality by combining qualified malloc and free/realloc calls found in counted loops into a single system call and hoisting out the single call and placing it immediately preceding the beginning of the counted loops. As a result of the application of the malloc-combining optimization results in improved cache locality allows for prefetching array pointers and data elements of the dynamic arrays as if the dynamic arrays were static.

6833862, Dec 21, 2004

Jun 30, 1999

09/345167

Wei Li - Cupertino CA

Logitech, Inc. - CA

H04N 5225

34820799, 348241, 358461

A method and apparatus for constructing an inexpensive camera with vignetting correction in the camera electronic hardware. The hardware is programmable through the use of a register storing a constant value corresponding to the amount of vignetting of a particular lens used in the camera. The register value is provided to a correction circuit which implements an algorithm that corrects for the amount of vignetting of pixels depending upon the pixel position.

6876263, Apr 5, 2005

Mar 5, 2003

10/382638

Wei Li - San Diego CA, US
Thomas Clark Bryan - San Diego CA, US
Harry Huy Dang - San Diego CA, US
Mehmet Mustafa Eker - Santee CA, US

Applied Micro Circuits Corporation - San Diego CA

H03B027/00

331 49, 331 46, 331185, 331175, 331 2, 331 16

A voltage-controlled oscillator (“VCO”) structure includes a plurality of VCO circuits, each having a different nominal operating frequency range. Power consumption of the VCO structure is regulated by selective activation/deactivation of the individual VCO circuits. In a preferred embodiment, only one of the VCO circuits is active at any given time. The active VCO can be selected to satisfy the requirements of the particular application and/or to compensate for semiconductor manufacturing process variations.

6911871, Jun 28, 2005

Mar 11, 2003

10/387014

Wei Li - San Diego CA, US
Thomas Clark Bryan - San Diego CA, US
Zhixiang Jason Liu - San Diego CA, US

Applied Micro Circuits Corporation - San Diego CA

H03B027/00

331 57, 331 34, 331185, 327276, 327281

A ring oscillator stage includes two differential transistor pairs configured to add an adjustable amount of delay to a differential input signal. Each differential pair is biased with a bias current transistor; the bias current transistor is “protected” by a voltage-clamping transistor that limits the drain voltage of the bias current transistor. The voltage-clamping transistors enable use of a power supply voltage (V) that would otherwise exceed the reliability breakdown voltage limit of the bias current transistors.

6995794, Feb 7, 2006

May 18, 2001

09/861279

Mark Hsu - Fremont CA, US
Mitchell Norcross - Harvard MA, US
Georges Auberger - Emerald Hills CA, US
Remy Zimmermann - Belmont CA, US
Sergio Maggi - San Mateo CA, US
George Sanchez - Fremont CA, US
Bryed Billerbeck - Mountain View CA, US
Wei Li - Cupertino CA, US
Jean-Michel Junien Labrousse - Belmont CA, US

Logitech Europe S.A. - Romanel-sur-Morges

H04N 5/217
H04N 9/64

348241, 348243

A low cost camera by implementing the major functions in host software is provided. This is accomplished by sending raw, digitized data from the camera directly to the host. The increased volume of raw data is handled by either an improved compression/decompression scheme using lossless compression, using lossy compression or using a shared bus with higher bandwidth. By moving such functions as color processing and scaling to the host, the pixel correction can also be moved to the host. This in turn allows the elimination of the frame buffer memory from the camera. Finally, the camera can use a low cost lens by implementing vignetting, distortion, gamma or aliasing correction with a correction value stored in a register of the camera for later access by the host to perform corrections.