Inventors:
Qifan Huang - Sunnyvale CA, US
Yu T. Tian - Palo Alto CA, US
Assignee:
Micronas USA, Inc. - Santa Clara CA
International Classification:
H04N 1/393
H04N 7/01
US Classification:
348581, 348441, 348704, 348561, 348625, 348627, 382298, 345472, 345660
Abstract:
Techniques for performing combined scaling, filtering, and/or scan conversion are disclosed that reduce that amount of line buffer space required in the overall design of a video processing system. In particular, coefficients from all or a sub-set of the scaling, filtering (smoothing/sharpening), and scan conversion filters are combined into one representative coefficient that can be applied in a single generic algorithm. Thus, implementation costs are reduced, particularly in system-on-chip implementations.