Search

Thao P Vo

from San Jose, CA
Age ~50

Thao Vo Phones & Addresses

  • 1933 Edgecrest Dr, San Jose, CA 95122
  • Rochester, MN
  • 9182 La Colonia Ave, Fountain Valley, CA 92708 (714) 842-8458 (714) 847-2335
  • Huntington Beach, CA
  • Westminster, CA
  • Garden Grove, CA
  • Santa Clara, CA
  • Midway City, CA

Professional Records

License Records

Thao P. Vo

License #:
M2-E002746 - Active
Category:
Cosmetology and Barbering
Type:
Nail Technician

Real Estate Brokers

Thao Vo Photo 1

Thao Vo, San Jose CA Agent

View page
Work:
Realty World - Six Sigma
San Jose, CA
(408) 482-4063 (Phone)
License #01912686
About:
As a full time professional real estate agent, I pride myself on offering superior personal service before, during and after your transaction. Knowledge, commitment, honesty, expertise and professionalism are the cornerstone of my business. Let me earn your trust, your business and most importantly your friendship. Don’t make another move without me. I guarantee you will see the difference quality service makes. I look forward to working with you!

Resumes

Resumes

Thao Vo Photo 2

Staff Specialist

View page
Location:
San Jose, CA
Industry:
Accounting
Work:
City of San José
Staff Specialist

San Jose State University
Accounting Associate

San Jose State University Nov 2015 - Jan 2016
Accountant I

San Jose Public Library Mar 2013 - Jan 2016
Library Page

San Jose State University May 2014 - Oct 2015
Accounting Assistant
Education:
San Jose State University 2012 - 2015
Bachelors, Bachelor of Science, Accounting
Evergreen Valley College 2008 - 2011
Associates, Associate of Arts, Business Management, Accounting
Skills:
Microsoft Excel
Microsoft Word
Microsoft Office
Powerpoint
Data Entry
Teamwork
Time Management
Accounting
Libraries
Peoplesoft
Sage 100 Erp
Blackbaud
Journal Entries
Accounts Payable
Languages:
English
Vietnamese
Thao Vo Photo 3

Thao Vo

View page
Location:
San Jose, CA
Education:
San Jose State University 2011 - 2014
Thao Vo Photo 4

Thao Vo

View page
Location:
San Jose, CA
Education:
(Ust) University of Science and Technology, Korea 2017 - 2018
Doctorates, Doctor of Philosophy, Philosophy
Thao Vo Photo 5

Marketing + Public Relations Assistant

View page
Industry:
Marketing And Advertising
Work:
Soirée Agency
Marketing + Public Relations Assistant
Thao Vo Photo 6

Thao Vo

View page
Location:
United States
Thao Vo Photo 7

Thao Vo

View page
Location:
United States
Thao Vo Photo 8

Thao Vo Milpitas, CA

View page
Work:
HGST - A Western Digital Company

Jul 2013 to 2000
Manufacturing Supervisor Cell Director

Grinding and Dicing Servicing, Inc
San Jose, CA
2010 to 2013
Fab Tech

FormFactor Inc
Livermore, CA
2006 to 2008
Jr. Process/ Manufacturing Engineer

Wells Fargo Bank
Mountain View, CA
2002 to 2006
Lead Teller, Customer Sales & Service Representative

Skills:
Pro-E, Pro/M analysis JMP 5.1 Analysis Financial Accounting Power Point AutoCad 2006 C programming Business Statistics Excel
Thao Vo Photo 9

Thao Vo Milpitas, CA

View page
Work:
HGST - A Western Digital Company

Jul 2013 to 2000
Manufacturing Supervisor

Grinding and Dicing Servicing, Inc
San Jose, CA
2010 to 2013
Fab Tech

FormFactor Inc
Livermore, CA
2006 to 2008
Jr. Process/ Manufacturing Engineer

Wells Fargo Bank
Mountain View, CA
2002 to 2006
Lead Teller, Customer Sales & Service Representative

Skills:
Semiconductor STEM (SEM) processes including Lamella FIB, liftout and microscopy imaging.

Business Records

Name / Title
Company / Classification
Phones & Addresses
Thao Thanh Vo
President
Facetime Realty Inc
Real Estate Agent/Manager · Real Estate Agents and Managers
1619 S Main St, Milpitas, CA 95035
2284 Fallingtree Dr, San Jose, CA 95131
Thao Vo
DRAGON SUPERMARKET LLC
Thao Vo
Principal
Wellness Center
Health/Allied Services
7720 Elmdale Way, Stanton, CA 90680
Thao Vo
EXPERT NAILS LLC

Publications

Us Patents

Method Of Failure Analysis With Cad Layout Navigation And Fib/Sem Inspection

View page
US Patent:
55612938, Oct 1, 1996
Filed:
Apr 20, 1995
Appl. No.:
8/425110
Inventors:
Yeng-Kaung Peng - Saratoga CA
Thao H. Vo - Santa Clara CA
Paul M. Wong - Milpitas CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01J 3700
US Classification:
250307
Abstract:
A method of analyzing a failure of a sample, such as a wafer or a package unit made from a die sliced from the wafer, uses a computer aided design (CAD) tool in conjunction with a dual beam scanner and reverse engineering to improve the yield of the product. The computer aided design tool provides navigation to a location of interest over a layout of a wafer sample which has failed a test. The location of interest of the sample is then inspected using the dual beam scanner. The inspection may be made with either a focused ion beam scan or with a scanning electron microscope scan to provide different types of scan images and information. After inspection, a reverse engineering process (stripping back) is performed on the sample and the sample is inspected again to determine the cause of the failure of the sample. Once the cause of the failure is determined, the manufacturing process can be changed to improve the yield of the wafers.

Real-Time In-Line Defect Disposition And Yield Forecasting System

View page
US Patent:
55983413, Jan 28, 1997
Filed:
Mar 10, 1995
Appl. No.:
8/401490
Inventors:
Zhi-Min Ling - San Jose CA
Thao Vo - San Jose CA
Siu-May Ho - San Jose CA
Ying Shiau - San Jose CA
Yeng-Kaung Peng - Saratoga CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1900
US Classification:
36446817
Abstract:
A real-time in-line defect disposition and yield forecasting system for a semiconductor wafer having layer containing devices includes an in-line fabrication inspection tool, a design review station, and a yield management station. The in-line fabrication inspection tool inspects at least two layers of the semiconductor wafer and produces first information including particle size, particle location and number of particles introduced therein for each of these layers. The design review station inspects the layers of the semiconductor wafer and produces second information including layouts of each of the layers. The yield management station is operatively connected to the in-line fabrication inspection tool and to the design review station. The yield management station retrieves the first information and the second information from the in-line fabrication inspection tool and from the design review station. The yield management station determines at least one of a number of killer defects for the devices in each of the layers or a defect sensitive area index for each of the layers using the first and second information.
Thao P Vo from San Jose, CA, age ~50 Get Report