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Chinh Q Vo

from San Jose, CA
Age ~50
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Also known as:
Chinh Quoc Vo, Chinh G Vo, Vo Chinh Quoc, Quoc Vo, Quoc Vo Chinh
Phone and address:
3802 Ashton Ct, San Jose, CA 95111
(408) 360-9570
Related to:
Phuong D Vo, 62Thanh Vo, 65Lusia Vo, 59Vu H Tang, 52Hanh Vo, 52
Connected to:
Aimy T Vo, 36Alice Vo, 70Allen Vo, 58Amijane O Vo, 56Anna T Vo, 42Arnold B Vo, 27Au T Vo, 37Barbara N Vo, 28Ca V Vo, 39Christie K Vo, 65

Chinh Vo Phones & Addresses

  • 3802 Ashton Ct, San Jose, CA 95111 (408) 360-9570
  • Gold River, CA
  • Sacramento, CA
  • 5460 Foothill Blvd, Oakland, CA 94601 (510) 436-7943

Work

Company: Andersen benjamin o Address: 385 Grand Ave Ste 200, Oakland, CA 94610 Phones: (510) 465-1679 Position: Owner Industries: Legal Services

Education

School / High School: University of California, Hastings College of The Law

Ranks

Licence: California - Active Date: 1995

Professional Records

Lawyers & Attorneys

Chinh Vo Photo 1

Chinh Trung Vo, Oakland CA - Lawyer

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Address:
385 Grand Ave Ste 300, Oakland, CA 94610
(510) 836-2508 (Office)
Licenses:
California - Active 1995
Education:
University of California, Hastings College of The Law
Graduated - 1995
University of California - Riverside
Specialties:
Intellectual Property - 20%
Litigation - 20%
Arbitration - 20%
Mediation - 20%
Personal Injury - 20%

Business Records

Name / Title
Company / Classification
Phones & Addresses
Chinh Vo
Owner
Andersen Benjamin O
Legal Services
385 Grand Ave Ste 200, Oakland, CA 94610
Chinh T. Vo
Owner
Chinh T. Vo, Law Firm
Legal Services Office
385 Grand Ave, Oakland, CA 94610
(510) 836-2508
Chinh Vo
Owner
Andersen Benjamin O
Offices of Lawyers
385 Grand Ave STE 200, Oakland, CA 94610
(510) 465-1679
Chinh T. Vo
Heinsenberg Investments LLC
1110 Franklin St, Oakland, CA 94607
Chinh Vo
Owner
Andersen Benjamin O
Legal Services
385 Grand Ave Ste 200, Oakland, CA 94610

Publications

Us Patents

Method And Apparatus For Programming Auto Shut-Off

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US Patent:
8116145, Feb 14, 2012
Filed:
Aug 29, 2008
Appl. No.:
12/202048
Inventors:
Pearl P. Cheng - Los Altos CA, US
Harry S. Luan - Saratoga CA, US
Chinh Vo - San Jose CA, US
Chih-Chieh (Steve) Wang - Fremont CA, US
Assignee:
Kilopass Technology, Inc. - Santa Clara CA
International Classification:
G11C 7/00
US Classification:
36518907, 36518518
Abstract:
A method and system for enabling auto shut-off of programming of a non-volatile memory cell is disclosed. The system includes a memory array having a plurality of memory cells, each cell storing one bit of data. During the programming process, programming signals are applied to the target memory cells. A predefined period of time after the programming signals are applied, the auto shut-off system begins sensing an output signal from the memory cell. After the system detects an output signal from the memory cell, the system waits for a second predefined period of time before turning off the programming voltages. The system may be configured to sense an output voltage from the memory cell. The system then compares the output voltage to a reference voltage in order to detect when the cell is programmed. Alternatively, the system may sense an output current from the memory cell. The system then compares the output current to a reference current to detect when the cell is programmed.

Reducing Bit Line Leakage Current In Non-Volatile Memories

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US Patent:
20090080275, Mar 26, 2009
Filed:
Sep 20, 2007
Appl. No.:
11/858515
Inventors:
Chinh Vo - San Jose CA, US
Harry Shengwen Luan - Saratoga CA, US
Pearl Cheng - Los Altos CA, US
International Classification:
G11C 7/02
US Classification:
365206
Abstract:
In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.

System Idle Time Reduction Methods And Apparatus

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US Patent:
20210397372, Dec 23, 2021
Filed:
Jun 22, 2020
Appl. No.:
16/907411
Inventors:
- Addison TX, US
Nihal Singla - Bangalore, IN
Chinh Vo - San Jose CA, US
Assignee:
SanDisk Technologies LLC - Addison TX
International Classification:
G06F 3/06
H01L 25/18
H01L 23/00
G11C 16/04
G11C 16/10
Abstract:
An apparatus is provided that includes a memory die including a pipeline circuit coupled to a memory structure. The memory die is configured to execute a first command by receiving in the pipeline circuit data to be written to the memory structure, processing the received data in the pipeline circuit and providing the processed data to the memory structure, predicting that the pipeline circuit has completed processing the received data, and ending execution of the first command based on the prediction.

Circuit For Low-Dropout Regulator Output

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US Patent:
20180095489, Apr 5, 2018
Filed:
Sep 30, 2016
Appl. No.:
15/283232
Inventors:
- San Jose CA, US
Chinh Vo - San Jose CA, US
International Classification:
G05F 1/575
Abstract:
An output circuit at the output of an LDO regulator has two FETs (Field-Effect Transistors), a current source and a capacitor. The first FET is connected to the LDO output and a second voltage supply. The second FET is connected in series with the current source between the LDO output and the second voltage supply. The second FET is connected to the first FET in such a matter that a bias voltage is supplied to the first FET so that in static conditions the first FET draws predetermined amounts of current from the LDO output and to divert the predetermined amounts of current to the LDO output or to draw additional amounts of current from the LDO output to compensate for transient currents on the LDO output and to reduce variations in the output voltage of the LDO regulator. The capacitor with the current source defines a time constant to control the recovery of the output circuit from sudden drops or rises in voltage at the LDO regulator output to allow the LDO regulator to respond without adverse effect to the LDO output voltage.

High-Speed Differential Current Sensing Of Preprogrammed Nvm Cells

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US Patent:
20180096730, Apr 5, 2018
Filed:
Sep 30, 2016
Appl. No.:
15/283195
Inventors:
- San Jose CA, US
Chinh Vo - San Jose CA, US
International Classification:
G11C 17/18
G11C 17/16
Abstract:
A differential current sensing circuit architecture is used with an integrated circuit NVM memory block in which a selected memory cell and a related complementary memory cell are accessed at the same time for reading. The circuit architecture is used not only for normal operations for reading the logic states of a selected memory cell and its complementary memory cell after programming, but also for reading the logic states of a selected memory cell and its complementary memory cell before programming for the detecting of faults in memory cells.
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Chinh Q Vo from San Jose, CA, age ~50 Get Report