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Susan Li

from San Francisco, CA
Deceased
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Related to:
Terry W Gong, 76Anna Luy JopSimon Luy, 73Simon J Luy, 34Corinne Ching, 74Jerry Li, 76Roland D Lee, 76Henry LiEdward H Li, 84Alexander D Li, 34
Connected to:
Ai Q Li, 64Ai H Li, 81Aida Li, 67Aijun Li, 65Aiwen Q Li, 56Aiyan Li, 61Alan Li, 80Alice Li, 46Alida Li, 59Alisha Li, 31

Susan Li Phones & Addresses

  • 380 25Th Ave, San Francisco, CA 94121 (415) 386-5339

Resumes

Resumes

Susan Li Photo 1

Susan Li Cupertino, CA

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Work:
Trimble Navigation LTD
Sunnyvale, CA
Nov 2012 to May 2013
Sr Mechanical Engineer 3
Newport Corporation
Santa Clara, CA
Apr 2008 to Aug 2012
Sr. Mechanical Engineer
Ultra Clean Technology Inc
Hayward, CA
Apr 2006 to 2008
Mechanical Engineer
Revera Inc
Santa Clara, CA
Jul 2004 to Apr 2006
Mechanical Engineer
Riverstone Networks Inc
Santa Clara, CA
May 1999 to Oct 2001
Mechanical Engineer
Insync Systems Inc
Milpitas, CA
Aug 1996 to May 1999
Mechanical Engineer
Education:
University of Notre Dame
South Bend, IN
1996
M.S. in Mechanical Engineering
Jiao Tong University
1992
B.S. in Materials Engineering

Business Records

Name / Title
Company / Classification
Phones & Addresses
Ms. Susan Li
Manager
Cable Link
Electronic Equipment & Supplies-Dealers
2525 Carling Avenue, Unit 16, Ottawa, ON K2B 7Z2
(613) 709-3083
Susan Li
Manager
Cable Link
Electronic Equipment & Supplies-Dealers
(613) 709-3083

Publications

Us Patents

Method For Modifying A C4 Semiconductor Device

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US Patent:
6468917, Oct 22, 2002
Filed:
Feb 10, 2000
Appl. No.:
09/502916
Inventors:
Susan Xia Li - Fremont CA
Arnold Louie - Cupertino CA
Maria Guardado - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21302
US Classification:
438712, 438714, 438723, 438725, 438745
Abstract:
The present invention provides a method for modifying a C4 device, the device including a circuit, a polyimide layer, and a plurality of solder bumps in the active region of the C4 device. The method includes removing the polyimide layer using a plasma etch, the plasma etch comprising a mixture of oxygen and an inert gas; modifying the circuit; and cleaning the modified C4 device with a reactive flux. By mixing the oxygen with an inert gas, the oxidation of the solder bumps due to the plasma etch are reduced. Because the top layer features are now readily visible, circuit structures are more easily located, and modification can be more easily performed and with more accuracy. In the preferred embodiment, the device is then cleaned with a reactive flux, which removes any oxidation layer which has formed on the solder bumps. In this manner, circuit modification may be performed more quickly while also minimizing the oxidation of the solder bumps. The reduced oxidation of the solder bumps will help the C4 packaging process to be successful for electrical testing after focused beam ion (FIB) modification.

Method For Isolating A Failure Site In A Wordline In A Memory Array

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US Patent:
7319623, Jan 15, 2008
Filed:
Nov 4, 2004
Appl. No.:
10/981026
Inventors:
Caiwen Yuan - Union City CA, US
Susan Xia Li - Fremont CA, US
Andy Gray - San Jose CA, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
G11C 7/00
US Classification:
365201, 714718, 714720
Abstract:
According to one exemplary embodiment, a method for isolating a failure site in a leaky wordline in a memory array includes dividing said leaky wordline into an initial leaky wordline portion and an initial non-leaky wordline portion, where the initial leaky wordline portion has wordline-to-substrate leakage. The initial leaky wordline portion can be determined by using a passive voltage contrast procedure to illuminate the initial leaky wordline portion. The method further includes performing a number of division and identification cycles on the initial leaky wordline portion to determine a final leaky wordline portion. According to this exemplary embodiment, the final leaky wordline portion comprises a predetermined number of memory cells. The method further includes performing a cutting and imaging procedure on the final leaky wordline portion to isolate the failure site.

Decapsulation Techniques For Multi-Chip (Mcp) Devices

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US Patent:
6358852, Mar 19, 2002
Filed:
May 17, 2000
Appl. No.:
09/574580
Inventors:
Susan Xia Li - Fremont CA
Mohammad Massoodi - Campbell CA
Daniel Yim - Fremont CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2100
US Classification:
438690, 216 67, 216 88, 438691, 438692, 438710
Abstract:
Aspects for performing decapsulation of multi-chip devices are presented. One aspect includes removing a top die of the multi-chip device without employing a wet chemical etch and removing residual attach and package materials to expose a bottom die of the multi-chip device. An alternate aspect includes utilizing mechanical polishing and wet chemical etching to remove a top die of the multi-chip device, and exposing a bottom die through chemical decapsulation to allow failure analysis of the bottom die. A Flash memory die as a top die and a static random access memory (SRAM) die as a bottom die are included as a multi-chip device capable of decapsulation through these aspects.
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Susan Li from San Francisco, CADeceased Get Report