Sun Yee Chan from 423 7Th St UNIT 106, Oakland, CA 94607, age 76

Inter-Procedural Allocation Of Stacked Registers For A Processor

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US Patent:

7120775, Oct 10, 2006

Filed:

Dec 29, 2003

Appl. No.:

10/747426

Inventors:

Yang Liu - Beijing, CN
Sun Chan - Fremont CA, US
Guangrong Gao - Beijing, CN
Zhaoqing Zhang - Beijing, CN

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711170, 711100, 711154, 711156, 711165, 712202, 712228

Abstract:

A method for an allocation of stacked registers for Intel's Itanium processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.

Optimization Based On Simulated Linking

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US Patent:

20040194073, Sep 30, 2004

Filed:

Mar 27, 2003

Appl. No.:

10/401994

Inventors:

Sun Chan - Fremont CA, US
Knud Kirkegaard - San Jose CA, US
David Sehr - Cupertino CA, US
Richard Tobacco - Santa Clara CA, US

International Classification:

G06F009/45
G06F009/44

US Classification:

717/151000, 717/162000

Abstract:

Identifying at least one unresolved symbol referenced in a first program component during a compilation phase of the first program component, searching a second program component that comprises object code, for a definition of the unresolved symbol, and selecting a type of compiler optimization for at least the first program component based at least in part on the results of the search of the second program component.

Shaping Data Packet Traffic

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US Patent:

20140029500, Jan 30, 2014

Filed:

Dec 29, 2011

Appl. No.:

13/976110

Inventors:

Sai Luo - Beijing, CN
Shanshan Zheng - Beijing, CN
Li Shang - Beijing, CN
Xin Zhou - Beijing, CN
Chunxiao Lin - Beijing, CN
Sun Chan - Fremont CA, US

International Classification:

H04W 52/02

US Classification:

370311

Abstract:

According to some embodiments, a communication module may be configured to transmit data packet traffic and a management module may be configured to shape the data packet traffic transmitted by the communication module The management module may shape the data packet traffic by buffering data packets routed at different times to the communication module based on at least one power management factor.

Method, System, And Computer Program Product For Using Static Single Assignment Form As A Program Representation And A Medium For Performing Global Scalar Optimization

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US Patent:

63017040, Oct 9, 2001

Filed:

Jun 16, 1998

Appl. No.:

9/097672

Inventors:

Frederick Chow - Fremont CA
Sun Chan - Fremont CA
Peter Dahl - Cupertino CA
Robert Kennedy - Boulder Creek CA
Raymond Lo - Sunnyvale CA
Mark Streich - Fremont CA
Peng Tu - Union City CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 9445

US Classification:

717 9

Abstract:

A method, system, and computer product uses a hashed static single assignment (SSA) form as a program representation and a medium for performing global scalar optimization. A compiler, after expressing the computer program in SSA form, can perform one or more static single assignment (SSA)-based, SSA-preserving global scalar optimization procedures on the SSA representation. Such a procedure modifies, (i. e. , optimizes) the SSA representation of the program while preserving the utility of its embedded use-deprogram information for purposes of subsequent SSA-based, SSA-preserving global scalar optimizations. This saves the overhead expense of having to explicitly regenerate use-def program information for successive SSA-based, SSA-preserving global scalar optimizations.

System And Method To Efficiently Represent Aliases And Indirect Memory Operations In Static Single Assignment Form During Compilation

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US Patent:

57685967, Jun 16, 1998

Filed:

Apr 23, 1996

Appl. No.:

8/636605

Inventors:

Frederick Chow - Fremont CA
Sun Chan - Fremont CA
Raymond Lo - Sunnyvale CA
Mark Streich - Fremont CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 945

US Classification:

395709

Abstract:

A system and method for an optimizer of a compilation suite for representing aliases and indirect memory operations in static single assignment (SSA) during compilation of a program having one or more basic blocks of source code. The optimizer converts all scalar variables of said program to SSA form, wherein said SSA form includes a plurality of variable versions, zero or more occurrences of a. chi. function, zero or more occurences of a. phi. function, and zero or more occurrences of a. mu. function. The. chi. function,. phi. function, and. mu. function are inserted for the variable versions. The optimizer also determines whether a variable version can be renamed to a zero version, and upon such a determination, the optimizer renames the variable version to a zero version. The optimizer further converts all indirect variables of a program to SSA form, wherein the SSA form includes a plurality of virtual variable versions such that a virtual variable is assigned to an indirect variable, zero or more occurrences of a. chi. function, zero or more occurences of a. phi.

Compiler Having Automatic Common Blocks Of Memory Splitting

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US Patent:

58482750, Dec 8, 1998

Filed:

Jul 29, 1996

Appl. No.:

8/688020

Inventors:

Dror E. Maydan - Mountain View CA
Sun C. Chan - Fremont CA
James C. Dehnert - Palo Alto CA
Jack C. Carter - Cupertino CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1206
G06F 1208

US Classification:

395705

Abstract:

In a computer system having a cache memory and a main memory for storing data, a method for laying out blocks of data to minimize a number of memory transfers between the cache memory and the main memory. Memory layout normally occurs at link time, after all the source files have been compiled. The code is compiled with the assumption that the memory blocks can be optimally placed. The linker then determines whether there has been any memory violations. Memory violations are marked. All marked memory locations are then placed in a layout that satisfies adjacency requirements.

System And Method To Efficiently Represent Aliases And Indirect Memory Operations In Static Single Assignment Form During Compilation

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US Patent:

61311898, Oct 10, 2000

Filed:

Nov 26, 1997

Appl. No.:

8/979939

Inventors:

Frederick Chow - Fremont CA
Sun Chan - Fremont CA
Raymond Lo - Sunnyvale CA
Mark Streich - Fremont CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 945

US Classification:

717 9

Abstract:

A system and method for an optimizer of a compilation suite for representing aliases and indirect memory operations in static single assignment (SSA) during compilation of a program having one or more basic blocks of source code. The optimizer converts all scalar variables of said program to SSA form, wherein said SSA form includes a plurality of variable versions, zero or more occurrences of a. chi. function, zero or more occurences of a. phi. function, and zero or more occurrences of a. mu. function. The. chi. function,. phi. function, and. mu. function are inserted for the variable versions. The optimizer also determines whether a variable version can be renamed to a zero version, and upon such a determination, the optimizer renames the variable version to a zero version. The optimizer further converts all indirect variables of a program to SSA form, wherein the SSA form includes a plurality of virtual variable versions such that a virtual variable is assigned to an indirect variable, zero or more occurrences of a. chi. function, zero or more occurences of a. phi.

Method, System, And Computer Program Product For Performing Register Promotion Via Load And Store Placement Optimization Within An Optimizing Compiler

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US Patent:

6128775, Oct 3, 2000

Filed:

Jun 16, 1998

Appl. No.:

9/097713

Inventors:

Frederick Chow - Fremont CA
Robert Kennedy - Boulder Creek CA
Raymond Lo - Sunnyvale CA
Peng Tu - Union City CA
Sun C. Chan - Fremont CA

Assignee:

Silicon Graphics, Incorporated - Mountain View CA

International Classification:

G06F 945

US Classification:

717 9

Abstract:

A method, system, and computer program product for performing register promotion, that optimizes placement of load and store operations of a computer program within a compiler. Based on the observation that the circumstances for promoting a memory location's value to register coincide with situations where the program exhibits partial redundancy between accesses to the memory location, the system is an approach to register promotion that models the optimization as two separate problems: (1) the partial redundancy elimination (PRE) of loads and (2) the PRE of stores. Both of these problems are solved through a sparse approach to PRE. The static single assignment PRE (SSAPRE) method for eliminating partial redundancy using a sparse SSA representation representations the foundation in eliminating redundancy among memory accesses, enabling the achievement of both computational and live range optimality in register promotion results. A static single use (SSU) representation is defined allowing the dual of the SSAPRE algorithm, called SSUPRE, to perform the partial redundancy elimination of stores. SSUPRE is performed after the PRE of loads, taking advantage of the loads' having been converted into pseudo-register references so that there are fewer barriers to the movement of stores.