US Patent:
20160239065, Aug 18, 2016
Inventors:
VICTOR W. LEE - SANTA CLARA CA, US
DAEHYUN KIM - SAN JOSE CA, US
YUXIN BAI - SAN JOSE CA, US
SHIHAO JI - PORTLAND OR, US
SHENG LI - SANTA CLARA CA, US
DHIRAJ D. KALAMKAR - BANGALORE, IN
NAVEEN K. MELLEMPUDI - BANGALORE, IN
International Classification:
G06F 1/32
G06F 9/50
Abstract:
In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance information, and a power controller coupled to the plurality of cores, the power controller having a logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores. Other embodiments are described and claimed.