Qiang Li

6888410, May 3, 2005

Oct 10, 2003

10/683183

Qiang (Thomas) Li - Irvine CA, US

Broadcom Corp. - Irvine CA

H03F001/22
H03F001/52

330298, 330311

A power amplifier includes an input transistor, an input bias circuit, an output transistor, and a power down circuit. The input transistor includes a gate, a drain, and a source, wherein the source of the input transistor is coupled to a supply voltage return and the gate of the input transistor is operably coupled to receive an outbound radio frequency (RF) signal. The input bias circuit is operably coupled to provide an enabling bias voltage to the gate of the input transistor during transmit mode and to provide a disabling bias voltage to the gate of the input transistor during power down mode. The output transistor includes a gate, a drain, and a source, wherein the drain of the output transistor is coupled to provide an output of the power amplifier and the source of the output transistor is coupled to the drain of the input transistor. The power down circuit is operably coupled to provide an output enabling bias voltage to the gate of the output transistor during the transmit mode and to provide an output disabling bias voltage to the gate of the output transistor during the power down mode, wherein the output disabling bias voltage is of a value to distribute gate oxide stress between the input transistor and the output transistor.

7109801, Sep 19, 2006

Mar 1, 2005

11/069657

Qiang (Thomas) Li - Irvine CA, US

Broadcom Corporation - Irvine CA

H03F 1/52
H03F 3/45

330298, 330253, 330277, 330311

A power amplifier includes an input transistor, an output transistor, and circuitry. The input transistor includes an input, a first node, and a second node, wherein the second node of the input transistor is coupled to a supply voltage return and the input of the input transistor operably coupled to receive an outbound radio frequency (RF) signal. The output transistor includes an input, a first node, and a second node, wherein the first node of the output transistor is coupled to provide an output of the power amplifier, the second node of the output transistor is coupled to the first node of the input transistor. The circuitry is operably coupled to provide an enabling bias voltage to the input of the input transistor and to the input of the output transistor during the transmit mode and to provide a disabling bias voltage to the input of the input transistor and to the input of the output transistor during the power down mode, wherein the disabling bias voltage is of a value to distribute gate oxide stress between the input transistor and the output transistor.

7119631, Oct 10, 2006

May 12, 2004

10/844237

Jesus Alfonso Castaneda - Los Angeles CA, US
Qiang (Tom) Li - Irvine CA, US

Broadcom Corporation - Irvine CA

H03H 7/38

333 32, 330302, 330305

Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface may be made such that the ground and VDD potential levels are effectively brought onto the die of the chip such that a true ground potential is maintained within the chip. This off-chip LC circuit operates cooperatively with an on-chip decoupling capacitor to reduce the overall effective inductance of the bond wires employed to bring signal and voltage levels from the die to the chip exterior. This circuit ensures a relatively low impedance for a PA (Power Amplifier) that is implemented within chip thereby providing for improved performance.

7129803, Oct 31, 2006

Mar 16, 2004

10/802015

Shahla Khorram - Irvine CA, US
Qiang Li - Irvine CA, US
Jesus Alfonso Castaneda - Los Angeles CA, US

Broadcom Corporation - Irvine CA

H03H 7/42
H03H 11/28

333 25, 333177

A tuned transformer balun circuit includes a transformer balun, a first tuning capacitor, a second tuning capacitor, and a third tuning capacitor. A first plate of the first tuning capacitor is operably coupled to a first node of the differential winding and a second plate of the first tuning capacitor is operably coupled to a circuit ground. A first plate of the tuning capacitor is operably coupled to a second node of the differential winding and a second plate of the second tuning capacitor is operably coupled to the circuit ground. A first plate of the third tuning capacitor is operably coupled to a first node of the single-end winding and the second plate of the third tuning capacitor is operably coupled to transceiver radio frequency signals, wherein, based on loading of the single-ended winding and the differential winding, the first, second, and third tuning capacitors resonate with the transformer balun to provide efficient energy transfer from the transmitter section to the antenna.

7149492, Dec 12, 2006

Jul 30, 2004

10/902764

Qiang Li - Irvine CA, US

Broadcom Corporation - Irvine CA

H04B 1/26
H04B 1/18
H04B 1/06
H04B 7/00

455323, 4551771, 4552001, 4552321, 4552772

An improved method and apparatus for using common mode feedback to maintain a predetermined DC level for an intermediate frequency output signal. A common mode feedback capacitor-select switch module is operable to use a bandwidth control signal from a radio interface of a wireless device to selectively connect a plurality of common mode feedback capacitors to an operational amplifier, thereby generating a common mode feedback signal as an input to an active mixer conversion gain module. The predetermined combination of common mode feedback capacitors is used in combination with a plurality of bandwidth capacitors to generate an overall capacitance that maintains the bandwidth of the system at a predetermined value. A predetermined capacitance value is “shifted” from the bandwidth capacitor bank to the CMFB capacitor bank, thereby providing an overall ratio that maintains the bandwidth while defining a predetermined capacitance connected to the operational amplifier to generate a desired common mode feedback signal that maintains the phase margin of the output signal at a predetermined level.

7233211, Jun 19, 2007

Jan 24, 2005

11/041549

Qiang (Tom) Li - Irvine CA, US

Broadcom Corporation - Irvine CA

H03B 19/00

331 74, 331 51, 331 76, 327115, 327117

A divider for a local oscillator (LO) generator system of a phase locked loop (PLL) in a transceiver chip. The divider includes at least one divider unit. Each divider unit includes a frequency divider unit for receiving an input signal having an input frequency and for outputting an output signal having an output frequency which is approximately one half of the input frequency. Each divider unit also includes a resistor bank coupled between a voltage source and the frequency divider unit, and a current stirring unit for supplying current to the frequency divider unit. The resistance of the resistor bank and a magnitude of the current supplied by the current stirring unit are variable depending on the input frequency.

7283800, Oct 16, 2007

Jul 30, 2004

10/902765

Qiang Li - Irvine CA, US

Broadcom Corporation - Irvine CA

H04B 1/26
H04B 1/18
H04B 1/06
H04B 7/00

455323, 4551771, 4552001, 4552321, 4552772

An improved adaptive mixer for use in the down conversion module of a wireless transceiver. The adaptive mixer comprises a conversion gain module that is operable to receive a radio frequency signal and to generate an intermediate frequency that is provided to a radio interface in a wireless transceiver. The radio interface is operable to generate a gain control signal and a bandwidth control signal. The gain control signal is provided to a gain control module that is operable to select a combination of load resistance values that will provide a predetermined gain level for the output of the conversion gain module. Bandwidth control logic in the adaptive mixer uses the bandwidth control signal to operably connect a plurality of bandwidth control capacitors to the conversion gain module to control the bandwidth of the output signal. By selecting predetermined values for the load resistance and for the bandwidth control capacitors, the method and apparatus of the present invention makes it possible to generate an intermediate frequency output signal having a predetermined gain and a predetermined bandwidth.

7321273, Jan 22, 2008

Oct 9, 2006

11/539674

Jesus Alfonso Castaneda - Los Angeles CA, US
Qiang (Tom) Li - Irvine CA, US

Broadcom Corporation - Irvine CA

H03F 3/191

333 24R, 330302, 330305

Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface may be made such that the ground and VDD potential levels are effectively brought onto the die of the chip such that a true ground potential is maintained within the chip. This off-chip LC circuit operates cooperatively with an on-chip decoupling capacitor to reduce the overall effective inductance of the bond wires employed to bring signal and voltage levels from the die to the chip exterior. This circuit ensures a relatively low impedance for a PA (Power Amplifier) that is implemented within chip thereby providing for improved performance.