Qiang Te Li

6336174, Jan 1, 2002

Aug 9, 1999

09/370855

Qiang Li - Campbell CA
Jon F. Zahornacky - San Jose CA

Maxtor Corporation - Longmont CO

G06F 1200

711162, 711161, 714 6, 365228

A hardware assisted memory module (HAMM) is coupled to a conventional computer system. During normal operation of the computer system, the HAMM behaves like a conventional memory module. The HAMM, however, detects and responds to at least one of the following trigger events: 1) power failure, 2) operating system hang-up, or 3) unexpected system reset. Upon detection of a trigger event, the HAMM electronically isolates itself from the host computer system before copying digital information from volatile memory to nonvolatile memory. Once isolated, the HAMM takes its power from an auxiliary power supply. The HAMM can be configured to copy all or part of the digital information to nonvolatile memory. Upon either a request or at power-up, the HAMM copies the digital information from the nonvolatile memory into the volatile memory. If there is a normal computer shutdown, the operating system will first warn the HAMM before shutting down, thus precluding it from performing a backup operation.

6470170, Oct 22, 2002

May 16, 2001

09/858620

Hai Xing Chen - Toronto, CA
Qiang Li - Campbell CA, 95008

G09B 300

434350

A system for learning and examination training is disclosed. A student can log on the system through a website to review training history, to access a menu of levels of practice examinations of interest to him, and to select training exams on the website. During the examination, the student is able to indicate whether or not help is required at any given point or question. Without regard to whether or not the student believes help is required, all students are subject to a dynamic/interactive evaluation of responses in which a teacher who is on-line with the same website at the time of the student is able to intervene during an examination to invoke help options for the student. In the first instance, the teacher can intervene to change the exam level to either a lower or to a higher one. Among the help options available to a student during an examination within a given level are âauto coachâ in which the student is provided with hints and examples; an adaptive question selection in which variations of the same questions are drawn from a database; real time talk support in which the on-line teacher can communicate with the student at the time that this option is invoked; and a multi-solution select option in which a database presents multiple means of problem to accommodate or discover the learning style of the student. The student can be scored, timed and graded in a variety of modes both during and after the examination.

6552574, Apr 22, 2003

Mar 1, 2002

10/087604

Lei Wang - Sunnyvale CA
Qiang Li - Fremont CA
Jianbin Wu - Fremont CA

PicoNetics, Inc. - Fremont CA

H03K 19096

326 98, 326119

Dynamic low-power logic using recycled energy is disclosed. Logic circuits have a discharge path, a precharge path and a control circuit. The precharge path is a PMOS transistor coupled between the clock line and the output node of the circuit and configured to charge the output node to the logic high voltage of the clock line during a precharge phase. During an evaluation phase, the discharge path computes the desired logic function at the output node. A control circuit is connected between the output node and the clock line and to the gate of the precharge path transistor. The control circuit provides the proper gate drive, regardless of the voltage on the output node or the inputs to the discharge path, to guarantee that the precharge transistor fully charges the output node to the logic high voltage of the clock line, which provides recycled energy for operating the circuit.

6693462, Feb 17, 2004

May 3, 2002

10/139040

Lei Wang - Sunnyvale CA
Qiang Li - Fremont CA

Piconetics, Inc. - Fremont CA

H03K 19096

326 98, 326119

A logic circuit for evaluating a logic function while a signal on a clock input is a logic high. The logic circuit pre-discharges an output node to the logic low of the signal on the clock input and then charges the output node to logic high from the clock input when the logic function of the input is such as to require the output node to change state. The pre-discharge path is an n-channel transistor that is conductive only when the signal on the clock input is low. Also disclosed is a logic circuit that evaluates a logic function while a signal on the clock input is a logic high and while the signal on the clock input is a logic low, thereby permitting logic evaluations on both phases of the signal on the clock input.

6784696, Aug 31, 2004

Feb 19, 2003

10/371238

Lei Wang - Sunnyvale CA
Qiang Li - Fremont CA
Jianbin Wu - Fremont CA

Piconetics, Inc. - Fremont CA

H03K 19096

326 98, 326112

Dynamic low-power logic using recycled energy is disclosed. Logic circuits have a discharge path, a precharge path and a control circuit. The precharge path is a PMOS transistor coupled between the clock line and the output node of the circuit and configured to charge the output node to the logic high voltage of the clock line during a precharge phase. During an evaluation phase, the discharge path computes the desired logic function at the output node. A control circuit is connected between the output node and the clock line and to the gate of the precharge path transistor. The control circuit provides the proper gate drive, regardless of the voltage on the output node or the inputs to the discharge path, to guarantee that the precharge transistor fully charges the output node to the logic high voltage of the clock line, which provides recycled energy for operating the circuit.

6888410, May 3, 2005

Oct 10, 2003

10/683183

Qiang (Thomas) Li - Irvine CA, US

Broadcom Corp. - Irvine CA

H03F001/22
H03F001/52

330298, 330311

A power amplifier includes an input transistor, an input bias circuit, an output transistor, and a power down circuit. The input transistor includes a gate, a drain, and a source, wherein the source of the input transistor is coupled to a supply voltage return and the gate of the input transistor is operably coupled to receive an outbound radio frequency (RF) signal. The input bias circuit is operably coupled to provide an enabling bias voltage to the gate of the input transistor during transmit mode and to provide a disabling bias voltage to the gate of the input transistor during power down mode. The output transistor includes a gate, a drain, and a source, wherein the drain of the output transistor is coupled to provide an output of the power amplifier and the source of the output transistor is coupled to the drain of the input transistor. The power down circuit is operably coupled to provide an output enabling bias voltage to the gate of the output transistor during the transmit mode and to provide an output disabling bias voltage to the gate of the output transistor during the power down mode, wherein the output disabling bias voltage is of a value to distribute gate oxide stress between the input transistor and the output transistor.

7009427, Mar 7, 2006

May 8, 2002

10/142740

Lei Wang - Sunnyvale CA, US
Qiang Li - Fremont CA, US
Jianbin Wu - Fremont CA, US

PicoNetics, Inc. - Fremont CA

H03K 19/096

326 95, 326119

A low power dynamic circuit with an inverter-like output is disclosed. The dynamic circuit includes a precharge circuit, a discharge circuit, and an output circuit. The precharge circuit charges a precharge node from the clock signal when the data input signal is low and the clock input is high. The discharge circuit discharges a discharge node to the clock signal when the data input signal is high and the clock input is low. The output circuit is an inverter-like configuration that uses the precharge node to generate a logic high and the discharge node to generate a logic low, as required by the data input signal. In one embodiment, the precharge circuit is operative with a first clock and the discharge circuit is operative with a second clock. In yet another embodiment, there is only a precharge circuit and an output circuit.

7109801, Sep 19, 2006

Mar 1, 2005

11/069657

Qiang (Thomas) Li - Irvine CA, US

Broadcom Corporation - Irvine CA

H03F 1/52
H03F 3/45

330298, 330253, 330277, 330311

A power amplifier includes an input transistor, an output transistor, and circuitry. The input transistor includes an input, a first node, and a second node, wherein the second node of the input transistor is coupled to a supply voltage return and the input of the input transistor operably coupled to receive an outbound radio frequency (RF) signal. The output transistor includes an input, a first node, and a second node, wherein the first node of the output transistor is coupled to provide an output of the power amplifier, the second node of the output transistor is coupled to the first node of the input transistor. The circuitry is operably coupled to provide an enabling bias voltage to the input of the input transistor and to the input of the output transistor during the transmit mode and to provide a disabling bias voltage to the input of the input transistor and to the input of the output transistor during the power down mode, wherein the disabling bias voltage is of a value to distribute gate oxide stress between the input transistor and the output transistor.