Min Xu

7522010, Apr 21, 2009

Apr 30, 2007

11/797081

Kevin YiKai Liang - Cupertino CA, US
Arvind Bomdica - Fremont CA, US
Min Xu - Mountain View CA, US
Ming So - Danville CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H03C 1/00

331185, 331176, 331182

An ultra-low power crystal oscillator architecture that draws less than 2 μA during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 μA.

7714615, May 11, 2010

Feb 18, 2008

12/032741

Yikai Liang - Cupertino CA, US
Arvind Bomdica - Fremont CA, US
Min Xu - Mountain View CA, US
Ming-Ju Lee - San Jose CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H03K 19/094

326 83, 326 27

A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.

7844954, Nov 30, 2010

Mar 27, 2008

12/057282

Ganesh Venkitachalam - Mountain View CA, US
Michael Nelson - Alamo CA, US
Boris Weissman - Mountain View CA, US
Min Xu - Palo Alto CA, US
Vyacheslav V. Malyugin - Los Gatos CA, US

VMware, Inc. - Palo Alto CA

G06F 9/44

717130, 717132, 717135

A method and computer program product for logging non-deterministic events of a virtual machine executing a sequence guest instructions, the method including tracking an execution point in the sequence of executing guest instructions, the tracking of the execution point including determining a branch count of executed branch instructions; and detecting an occurrence of a non-deterministic event directed to the virtual machine during execution of the sequence of guest instructions, and recording information which includes an identifier of a current execution point, wherein the identifier includes the branch count.

8102632, Jan 24, 2012

Mar 18, 2009

12/406684

Yikai Liang - Cupertino CA, US
Arvind Bomdica - Fremont CA, US
Samudyatha Suryanarayana - Sunnyvale CA, US
Gayatri Gopalan - Sunnyvale CA, US
Min Xu - Mountain View CA, US
Xin Liu - El Dorado Hills CA, US
Ming-Ju Edward Lee - San Jose CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H02H 9/00
H01C 7/12
H02H 1/00
H02H 1/04
H02H 3/22
H02H 9/06

361 56, 361118

Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.

8102633, Jan 24, 2012

Mar 18, 2009

12/406705

Yikai Liang - Cupertino CA, US
Arvind Bomdica - Fremont CA, US
Samudyatha Suryanarayana - Sunnyvale CA, US
Gayatri Gopalan - Sunnyvale CA, US
Min Xu - Mountain View CA, US
Xin Liu - El Dorado Hills CA, US
Ming-Ju Edward Lee - San Jose CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H02H 9/00
H01C 7/12
H02H 1/00
H02H 1/04
H02H 3/22

361 56, 361118

Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.

8201169, Jun 12, 2012

Jun 15, 2009

12/484640

Ganesh Venkitachalam - Mountain View CA, US
Rohit Jain - Mountain View CA, US
Boris Weissman - Mountain View CA, US
Daniel J. Scales - Mountain View CA, US
Vyacheslav Malyugin - Los Gatos CA, US
Jeffrey W. Sheldon - Mountain View CA, US
Min Xu - Palo Alto CA, US

VMware, Inc. - Palo Alto CA

G06F 9/455
G06F 9/46
G06F 11/00

718 1, 714 2, 714 11, 714 12, 714 13, 714 20, 718100

In a computer system running a primary virtual machine (VM) on virtualization software on a primary virtualized computer system (VCS) and running a secondary VM on virtualization software on a secondary VCS, a method for the secondary VM to provide quasi-lockstep fault tolerance for the primary VM includes: as the primary VM is executing a workload, virtualization software in the primary VCS is: (a) causing predetermined events to be recorded in an event log, (b) keeping output associated with the predetermined events pending, and (c) sending the log entries to the virtualization software in the secondary VCS; as the secondary VM is replaying the workload, virtualization software in the secondary VCS is: (a) sending acknowledgements indicating that log entries have been received; (b) when the virtualization software encounters one of the predetermined events, searching the log entries to determine whether a log entry corresponding to the same event was received from the primary VCS, and if so, comparing data associated with the predetermined event produced by the secondary VM with that of the primary VM; if there is a match, the virtualization software in the secondary VCS transmitting an acknowledgement to the virtualization software in the primary VCS; one of the virtualization software in the primary or secondary VCS dropping the event and the other dispatching the output; and if there is no match, performing a checkpoint resynchronization.

8289056, Oct 16, 2012

Dec 3, 2008

12/327787

Min Xu - Mountain View CA, US
Ming-Ju E. Lee - San Jose CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H03L 7/06

327156, 327159, 375373

Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating a substantially 270 degree phase shifted clock signal and a substantially 540 degree phase shifted clock signal, a phase detector receiving the system clock signal and the substantially 270 degree phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the substantially 270 degree phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.

8321842, Nov 27, 2012

Jun 27, 2008

12/163513

Min Xu - Palo Alto CA, US
Dmitry Grinberg - Mountain View CA, US
Vyacheslav Malyugin - Los Gatos CA, US
Petr Vandrovec - Mountain View CA, US
Ganesh Venkitachalam - Mountain View CA, US
Boris Weissman - Mountain View CA, US
Andrew Biggadike - Palo Alto CA, US
James Chow - San Jose CA, US

VMware, Inc. - Palo Alto CA

G06F 9/44
G06F 9/455

717127, 717124, 718 1

Replay-time-only functionalities in a computer program are executed only during replay in a virtual machine and are skipped outside of replay. If a replay-time-only functionality is detected during the replay of a program execution in a virtual machine, the replay may be paused and the virtual machine state may be saved. The replay-time-only core functionality is executed. When this execution is complete, a prior state of the virtual machine may be restored and the replay may be resumed.