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Mei Li Phones & Addresses

  • San Gabriel, CA

Professional Records

Medicine Doctors

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Mei Li

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Specialties:
Pathology
Anatomic Pathology & Clinical Pathology

License Records

Mei Li

License #:
1206013697
Category:
Nail Technician License

Lawyers & Attorneys

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Mei Li - Lawyer

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ISLN:
909973726
Admitted:
1989
Law School:
Beijing University, B.L., 1985

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mei Li
President
Wayne Holdings, Inc
Business Consulting Services
5250 W Century Blvd, Los Angeles, CA 90045
Mei Yu Li
President
Grace Trading Group
Whol Nondurable Goods
133 W Garvey Ave, Monterey Park, CA 91754
Mei Li
President
ANIMA INTERNATIONAL CORP
Mfg Misc Products
234 S 5 Ave, La Puente, CA 91746
234 S 5 Ave, Whittier, CA 91746
246 S 5 Ave, Whittier, CA 91746
246 S 5 Ave, La Puente, CA 91746
(626) 369-0281, (626) 369-0282
Mei Chun Li
President
KING CHAN INSURANCE SERVICES INC
Insurance Agent/Broker
9535 Broadway, Temple City, CA 91780
(626) 289-2856
Mei Li
Principal
Pbt Services
Services-Misc
5250 W Century Blvd, Los Angeles, CA 90045
Mei Q. Li
Principal
Valencia Israel
Ret Women's Clothing
748 S Atlantic Blvd, Los Angeles, CA 90022
Mei Xing Li
ROYAL BUFFET OF 1930 INC
Mei Li
Owner, Principal
Tm Distributor
Whol Nondurable Goods
808 Highland Ave, Glendale, CA 91202

Publications

Wikipedia References

Mei Li Photo 3

Mei Li

About:
Born:

31 March 1970 • Eindhoven , Netherlands

Work:
Position:

Dutch politician • Member of the House of Representatives of the Netherlands • Minister • Manager

Education:
Studied at:

University of Amsterdam

Area of science:

Higher education

Skills & Activities:
Ascribed status:

Dutch of Chinese descent • Indonesian of Chinese descent

Activity:

Labour Party of Netherlands politician

Preference:

Christianity • Liberalism • Social liberal

Sport:

Welfare

Master status:

Working part time

Us Patents

Radiation-Hard, Low Power, Sub-Micron Cmos On A Soi Substrate

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US Patent:
58077715, Sep 15, 1998
Filed:
Jun 4, 1996
Appl. No.:
8/658188
Inventors:
Truc Q. Vu - Signal Hill CA
Chen-Chi P. Chang - Newport Beach CA
James S. Cable - San Clemente CA
Mei F. Li - Mission Viejo CA
Assignee:
Raytheon Company - Lexington MA
International Classification:
H01L 2184
US Classification:
438154
Abstract:
A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both a fabrication and structural complexity favorably comparable to conventional CMOS devices which are not radiation-hard. A method for fabricating the device is disclosed.

Transistor Fabrication Method Using Dielectric Protection Layers To Eliminate Emitter Defects

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US Patent:
55232442, Jun 4, 1996
Filed:
Dec 19, 1994
Appl. No.:
8/359102
Inventors:
Truc Q. Vu - Signal Hill CA
Maw-Rong Chin - Huntington Beach CA
Mei F. Li - Mission Viejo CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 21265
H01L 4900
US Classification:
437 31
Abstract:
A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions. The dielectric etch stop (protection) layers (116, 130) are non-critically thick and are fully removed from above an extrinsic base region (142) of the device by wet etching before forming the emitter (152) and base regions (142, 144). The method results in a more uniform, lower resistance base connection, higher chip yields, more uniform device properties, and greater device reliability.
Mei Li from San Gabriel, CA Get Report