Mei Li Phones & Addresses
-
Chino, CA
-
Riverside, CA
-
31 Colorado St #E, Arcadia, CA 91007 (626) 828-2880
-
Northridge, CA
-
10405 Canoga Ave APT 237, Chatsworth, CA 91311
-
Alhambra, CA
Business Records
Name / Title
Company / Classification
Phones & Addresses
President
Wayne Holdings, Inc
Business Consulting Services
Business Consulting Services
5250 W Century Blvd, Los Angeles, CA 90045
President
Grace Trading Group
Whol Nondurable Goods
Whol Nondurable Goods
133 W Garvey Ave, Monterey Park, CA 91754
President
ANIMA INTERNATIONAL CORP
Mfg Misc Products
Mfg Misc Products
234 S 5 Ave, La Puente, CA 91746
234 S 5 Ave, Whittier, CA 91746
246 S 5 Ave, Whittier, CA 91746
246 S 5 Ave, La Puente, CA 91746
(626) 369-0281, (626) 369-0282
234 S 5 Ave, Whittier, CA 91746
246 S 5 Ave, Whittier, CA 91746
246 S 5 Ave, La Puente, CA 91746
(626) 369-0281, (626) 369-0282
President
KING CHAN INSURANCE SERVICES INC
Insurance Agent/Broker
Insurance Agent/Broker
9535 Broadway, Temple City, CA 91780
(626) 289-2856
(626) 289-2856
Principal
Pbt Services
Services-Misc
Services-Misc
5250 W Century Blvd, Los Angeles, CA 90045
Principal
Valencia Israel
Ret Women's Clothing
Ret Women's Clothing
748 S Atlantic Blvd, Los Angeles, CA 90022
ROYAL BUFFET OF 1930 INC
Owner, Principal
Tm Distributor
Whol Nondurable Goods
Whol Nondurable Goods
808 Highland Ave, Glendale, CA 91202
Publications
Us Patents
Split-Gate Flash Eeprom Cell And Array With Low Voltage Erasure
View pageUS Patent:
53434242, Aug 30, 1994
Filed:
Apr 16, 1993
Appl. No.:
8/047134
Inventors:
Chen-Chi P. Chang - Newport Beach CA
Mei F. Li - Mission Viejo CA
Mei F. Li - Mission Viejo CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 2968
G11C 1134
G11C 1134
US Classification:
365185
Abstract:
Each unit cell (10) of a flash EEPROM array (50) includes a control gate (38) having a section (38b) disposed in series between a program section (34a) of a floating gate (34) and a source (18) to provide threshold voltage control for erasure. The floating gate (34) further has an erase section (34b) which extends from the program section (34a) around an end of a channel (22) to the source (18). A thin tunnel oxide layer (32) is formed between an end portion (34c) of the erase section (34b) and an underlying portion of the source (18) which enables the floating gate (34) to be erased by Fowler-Nordheim tunneling from the end portion (34c) through the oxide layer (32) to the source (18) with low applied voltages.
Radiation-Hard, Low Power, Sub-Micron Cmos On A Soi Substrate
View pageUS Patent:
58077715, Sep 15, 1998
Filed:
Jun 4, 1996
Appl. No.:
8/658188
Inventors:
Truc Q. Vu - Signal Hill CA
Chen-Chi P. Chang - Newport Beach CA
James S. Cable - San Clemente CA
Mei F. Li - Mission Viejo CA
Chen-Chi P. Chang - Newport Beach CA
James S. Cable - San Clemente CA
Mei F. Li - Mission Viejo CA
Assignee:
Raytheon Company - Lexington MA
International Classification:
H01L 2184
US Classification:
438154
Abstract:
A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both a fabrication and structural complexity favorably comparable to conventional CMOS devices which are not radiation-hard. A method for fabricating the device is disclosed.
Manufacturing High Speed Low Leakage Radiation Hardened Cmos/Soi Devices
View pageUS Patent:
50249657, Jun 18, 1991
Filed:
Feb 16, 1990
Appl. No.:
7/481148
Inventors:
Chen-Chi P. Chang - Newport Beach CA
Mei Li - Mission Viejo CA
Mei Li - Mission Viejo CA
International Classification:
H01L 21336
US Classification:
437 57
Abstract:
A method of fabricating high speed, low leakage, radiation hardened integrated circuit semiconductor devices. In accordance with the method a SIMOX (separation by ion implantation of oxygen) wafer is masked with a separation mask to form silicon islands. The separation mask forms groups of N-channel and P-channel devices that are isolated from each other. The N- and P-channel device separation assists in preventing device latch-up. N- and N-channel devices are isolated by controlling the process due to high field inversion thresholds and radiation hardened field oxide to eliminate any channel-to-channel leakage current after high dosage irradiation. A relatively thin gate oxide layer is formed over the islands, and the island edges are covered with phosphoroborosilicate glass deposited at a relatively low temperature (850. degree. C. ) to eliminate sharp island edges and hence edge leakage. The use of SIMOX substrate materials, phosphoroborosilicate glass and thin oxide provides the benefits of improved speed and reduced leakage due to intrinsic oxide isolation, shallow wells and source and drain junctions.
High Speed Silicon-On-Insulator Device And Process Of Fabricating Same
View pageUS Patent:
50473565, Sep 10, 1991
Filed:
Feb 16, 1990
Appl. No.:
7/481032
Inventors:
Mei Li - Mission Viejo CA
Chen-Chi P. Chang - Newport Beach CA
Maw-Rong Chin - Huntington Beach CA
Chen-Chi P. Chang - Newport Beach CA
Maw-Rong Chin - Huntington Beach CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 2186
US Classification:
437 21
Abstract:
High speed silicon-on-insulator radiation hardened semiconductor devices and a method of fabricating same. Starting with a SIMOX wafer (10) having a layer of silicon (12) on a layer of buried oxide (11), P-well and N-well masks are aligned to an oversized polysilicon mask (16). This produces relatively thick source and drain regions (18) and relatively thin gate regions (17). The relatively thick source and drain regions (18) reduce the risk of dry contact etch problems. N-channel and P-channel threshold voltages are adjusted prior to the formation of active areas, thus substantially eliminating edge and back cannel leakage. A sacrificial thin oxide layer (21) is employed in fabricating the N-well and P-well implants so that both front and back channel threshold voltage adjustments are controlled. Good control of doping profiles is obtained, leading to excellent threshold voltage control and low edge and back channel leakages. The speed of devices fabricated using the method of the present invention is high due to reduced capacitances resulting from thinner silicon-on-insulator films.
Transistor Fabrication Method Using Dielectric Protection Layers To Eliminate Emitter Defects
View pageUS Patent:
55232442, Jun 4, 1996
Filed:
Dec 19, 1994
Appl. No.:
8/359102
Inventors:
Truc Q. Vu - Signal Hill CA
Maw-Rong Chin - Huntington Beach CA
Mei F. Li - Mission Viejo CA
Maw-Rong Chin - Huntington Beach CA
Mei F. Li - Mission Viejo CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 21265
H01L 4900
H01L 4900
US Classification:
437 31
Abstract:
A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions. The dielectric etch stop (protection) layers (116, 130) are non-critically thick and are fully removed from above an extrinsic base region (142) of the device by wet etching before forming the emitter (152) and base regions (142, 144). The method results in a more uniform, lower resistance base connection, higher chip yields, more uniform device properties, and greater device reliability.
Radiation-Hard, High-Voltage Semiconductive Device Structure Fabricated On Soi Substrate
View pageUS Patent:
51378370, Aug 11, 1992
Filed:
Aug 20, 1990
Appl. No.:
7/569304
Inventors:
Chen-Chi P. Chang - Newport Beach CA
Mei F. Li - Mission Viejo CA
Mei F. Li - Mission Viejo CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 21265
H01L 2170
H01L 2170
US Classification:
437 21
Abstract:
Highly doped N- and P-type wells (16a, 16b) in a first silicon layer (16) on an insulator layer (14) of a SIMOX substrate (10). Complementary MOSFET devices (52,54,58,62) are formed in lightly doped N- and P-type active areas (22a, 22b) in a second silicon layer (22) formed on the first silicon layer (16). Adjacent active areas (22a, 22b) and underlying wells (16a, 16b) are isolated from each other by trenches (36,78) filled with a radiation-hard insulator material. Field oxide layers (42,64) are formed of a radiation-hard insulator material, preferably boron phosphorous silicon dioxide glass, over the surface of the second silicon layer (22) except in contact areas (68) of the devices (52,54,58,62). The devices (52,54,58,62) are formed in the upper portions of the active areas (22a, 22b), and are insensitive to the interfacial states of the SIMOX substrate (10). The buried wells (16a, 16b ) under the active areas (22a, 22b) have low resistance and enable the devices (52,54,58,62) to have high snap-back voltages.
Nonvolatile Memory Device
View pageUS Patent:
56524480, Jul 29, 1997
Filed:
Aug 2, 1996
Appl. No.:
8/691475
Inventors:
Chen-Chi Peter Chang - Newport Beach CA
Mei F. Li - Mission Viejo CA
Truc Q. Vu - Signal Hill CA
Mei F. Li - Mission Viejo CA
Truc Q. Vu - Signal Hill CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 2976
US Classification:
257315
Abstract:
The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions. The fabrication process and thinness of the latch transistor gate improve the linewidth control of other transistors formed on the substrate and the latch transistor by avoiding overetching and reducing the normal etching time for the latch gate, respectively.
High Speed Silicon-On-Insulator Device
View pageUS Patent:
51403900, Aug 18, 1992
Filed:
Jan 28, 1991
Appl. No.:
7/646119
Inventors:
Mei Li - Mission Viejo CA
Chen-Chi P. Chang - Newport Beach CA
Maw-Rong Chin - Huntington Beach CA
Chen-Chi P. Chang - Newport Beach CA
Maw-Rong Chin - Huntington Beach CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 2701
US Classification:
357 237
Abstract:
High speed silicon-on-insulator radiation hardened semiconductor devices and a method of fabricating same. Starting with a SIMOX wafer (10) having a layer of silicon (12) on a layer of buried oxide (11), P-well and N-well masks are aligned to an oversized polysilicon mask (16). This produces relatively thick source and drain regions (18) and relatively thin gate regions (17). The relatively thick source and drain regions (18) educe the risk of dry contact etch problems. N-channel and P-channel threshold voltages are adjusted prior to the formation of active areas, thus substantially eliminating edge and back channel leakage. A sacrificial thin oxide layer (21) is employed in fabricating the N-well and P-well implants so that both front and back channel threshold voltage adjustments are controlled. Good control of doping profiles is obtained, leading to excellent threshold voltage control and low edge and back channel leakages. The speed of devices fabricated using the method of the present invention is high due to reduced capacitances resulting from thinner silicon-on-insulator films.