Li Li

6352192, Mar 5, 2002

Feb 29, 2000

09/515185

Tien-Yu Tom Lee - Phoenix AZ
James Vernon Hause - Maricopa AZ
Li Li - Gilbert AZ

Motorola, Inc. - Schaumburg IL

B23K 1005

228102, 228105, 2282621, 2281801

A system ( ) and method are used for predicting and controlling the temperature of a semiconductor wafer ( ) during a solder reflow process by controlling the operating profile of a solder reflow furnace ( ). The emissivity of the surface of the wafer ( ) is measured using an infrared device ( ) prior to the solder reflow process. Using the measured emissivity value of the wafer ( ), the peak temperature of the wafer ( ) is predicted, and the operating profile of the solder reflow furnace ( ) is adjusted accordingly to achieve a desired temperature profile of the wafer ( ). A process for reflowing solder on a semiconductor wafer calculates a predicted peak temperature of a semiconductor wafer ( ) and controls the actual temperature of the wafer ( ) during a solder reflow process by controlling the operating profile of a solder reflow furnace ( ).

6451127, Sep 17, 2002

Jun 1, 1999

09/323464

Li Li - Gilbert AZ
Treliant Fang - Chandler AZ

Motorola, Inc. - Schaumbrug IL

B23K 35363

148 23, 148 24

A conductive paste composition is described which comprises an alloy of tin and a flux composition. The flux composition comprises an aromatic carboxylic acid fluxing agent and a polymeric solvent.

6669079, Dec 30, 2003

Aug 2, 2002

10/211631

Li Li - Gilbert AZ
Treliant Fang - Chandler AZ

Motorola, Inc. - Schaumburg IL

B23K 3526

2282629, 148 23, 148 24

A conductive paste ( ) for use in making conductive bumps ( ) and a method for using the conductive paste to make conductive bumps ( ) on a substrate ( ). The conductive paste ( ) is formed by combining a tin alloy with a flux composition containing an aromatic carboxylic acid fluxing agent and a solvent. The conductive paste ( ) is disposed on underbump metallization layers ( ) and reflowed to form the conductive bumps ( ).

6841736, Jan 11, 2005

Sep 26, 2002

10/256789

Li Li - Gilbert AZ, US

Motorola, Inc. - Schaumburg IL

H01B 708

174117FF, 174117 R, 174117 AS

An embodiment of a current-carrying structure () includes a first electrically conductive layer () and a second electrically conductive layer (). The second electrically conductive layer is in contact with the first electrically conductive layer along substantially the entire length of the first electrically conductive layer. The second electrically conductive layer is above the first electrically conductive layer. A non-electrically conductive layer () is in contact with the first electrically conductive layer and the second electrically conductive layer. A current travels simultaneously through the first electrically conductive layer and the second electrically conductive layer.

7136274, Nov 14, 2006

Oct 28, 2004

10/975720

Robert B. Lempkowski - Elk Grove IL, US
Li Li - Scottsdale AZ, US

Motorola, Inc. - Schaumburg IL

H01G 4/228

3613063, 3613061, 3613211, 361767, 361794, 174 522, 174255, 174260

An embedded multilayer printed circuit includes a first ground plane () of a multilayer printed circuit board and an embedded layer. The embedded layer includes a co-planar capacitor (), a distributed inductor (), and a capacitive plate () circuit. The capacitive plate is a plate of a vertical capacitor (). The embedded layer further includes a node () of the embedded multilayer printed circuit that is formed by a connection of a first terminal of the co-planar capacitor and a first terminal of the first distributed inductor, and in some embodiments, the first capacitive plate is also connected to the node. A second terminal of one of the co-planar capacitor and the distributed inductor is connected to the first ground plane.

7446017, Nov 4, 2008

May 31, 2006

11/444091

Lianjun Liu - Chandler AZ, US
Philip H. Bowles - Fountain Hills AZ, US
Li Li - Scottsdale AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/30

438455, 438106, 438107, 438109, 257E21122, 257E21567

A patterned ground shield (PGS) () in a vertically-integrated structure includes a patterned conductor (e. g. , a metallic layer) provided between a first substrate () having a first semiconductor device ( formed therein and a second substrate () having a second device () formed therein. A bonding layer () is used to bond the vertically-integrated die and/or wafers. The PGS may be formed on a surface (e. g. , the backside) of the second (topmost) substrate, or may be formed over the first semiconductor device—for example, on a dielectric layer formed over the first semiconductor device. The PGS may consist of parallel stripes in various patterns, or may be spiral-shaped, lattice-shaped, or the like.

20080246126, Oct 9, 2008

Apr 4, 2007

11/696374

Philip H. Bowles - Fountain Hills AZ, US
Li Li - Scottsdale AZ, US
Lianjun Liu - Chandler AZ, US

FREESCALE SEMICONDUCTOR, INC. - Austin TX

H01L 23/552
H01L 21/58

257659, 438109, 257E23114, 257E21505

According to an example embodiment, a stacked die package includes a first die (), first active circuitry () disposed on an upper surface of the first die, and a first conductive pattern () disposed on the first active circuitry. The stacked die package further includes a second die () disposed over the first die, where the first die is wider than the second die in a cross-section of the stacked die package, second active circuitry () disposed on an upper surface of the second die, and a second conductive pattern () disposed on the second active circuitry. The stacked die package further includes a first wirebond () that connects the first conductive pattern to the second conductive pattern and a mold compound () disposed on the first die, the mold compound encapsulating the second die and the wirebond.

20110250721, Oct 13, 2011

Jun 21, 2011

13/165371

Philip H. Bowles - Fountain Hills AZ, US
Li Li - Scottsdale AZ, US
Lianjun Liu - Chandler AZ, US

FREESCALE SEMICONDUCTOR, INC. - Austin TX

H01L 21/50
H01L 21/78

438107, 438113, 257E21499, 257E21599

Embodiments include methods for forming a stacked die package with a first die, first active circuitry on an upper surface of the first die, and a first conductive pattern on the first active circuitry. The stacked die package further includes a second die stacked over the first die, where the first die is wider than the second die in a cross-section of the stacked die package, and second active circuitry is present on an upper surface of the second die. The stacked die package further includes a mold compound disposed on the first die, where the mold compound encapsulates the second die. Electrical connections are formed from the top surface of the mold compound to the first conductive pattern and the second active circuitry, and a conductive pattern on the top surface of the mold compound provides a continuous electrical connection between upper ends of the electrical connections.