Kee K Kim

6648891, Nov 18, 2003

Sep 14, 2001

09/961040

Kee D. Kim - Sacramento CA

The Regents of the University of California - Oakland CA

A61B 1756

606 69, 606102, 606105

The invention provides a fusion plate system, and method for installing this system upon a patients spine. The system uses a distractor device which measures an appropriately sized fusion plate for a corpectomy or discectomy application. Once a properly sized fusion plate is selected, the distractor device compresses the vertebrae and any associated bone graft placed between the vertebrae, thereby assuring maximum contact between the vertebrae and bone graft at a corpectomy or discectomy location. Compression is maintained by the distractor device while the fusion plate is anchored upon the corpectomy or discectomy site. Furthermore, the inventive fusion plate system and method results in the fusion plate being properly centered upon a patients spine, so that an aesthetically pleasing, as well as functional, surgical result is achieved.

6918074, Jul 12, 2005

Jun 28, 2002

10/187474

Kee Sup Kim - Folsom CA, US
Adarsh Kalliat - Kerala, IN
Ajith Prasad - Bangalore, IN

Intel Corporation - Santa Clara CA

G01R031/3177
G01R031/3187
G01R031/3193

714733, 714726

A testing device uses an input signature register to conduct “at speed” testing of asynchronous circuit responses in an effort to determine the operability of a monitored circuit. Upon receiving an enable signal, the input signature register quickly measures, compresses, and transmits the tested circuit responses so that the responses can be compared with a set of anticipated responses to determine whether the circuit is functioning properly. The enabled input signature register, such as a MISR or a SISR, generates an output signature, which contains the compressed responses of the monitored circuit and helps the testing device analyze circuit performance.

7185253, Feb 27, 2007

Mar 27, 2002

10/107628

Subhasish Mitra - Rancho Cordova CA, US
Kee Sup Kim - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G01R 31/28
G06F 17/50

714734, 716 2

Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.

7188284, Mar 6, 2007

Jun 30, 2004

10/882523

Subhasish Mitra - Rancho Cordova CA, US
Kee S. Kim - El Dorado Hills CA, US
Tak M. Mak - Union City CA, US
Prashant M. Goteti - Folsom CA, US

Intel Corporation - Santa Clara CA

G01R 31/28

714726, 714731

In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.

7240260, Jul 3, 2007

Dec 11, 2002

10/317605

Subhasish Mitra - Rancho Cordova CA, US
Kee Sup Kim - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G01R 31/3183
G01R 31/316

714726, 714724, 714752

In one embodiment, a method is provided. In the method of this embodiment, a stimulus signal set may be generated and supplied, as input, to first circuitry. Each respective stimulus signal in the stimulus signal set may be generated based at least in part upon a respective non-null subset of an input signal set. No two respective stimulus signals in the stimulus signal set may be generated based upon the same respective non-null subset of the input signal set. The stimulus signal set may include a respective number of stimulus signals that is greater than a respective number of input signals in the input signal set. Of course, many modifications, variations, and alternatives are possible without departing from the method of this embodiment.

7278074, Oct 2, 2007

Jan 26, 2005

11/044826

Subhasish Mitra - Folsom CA, US
Ming Zhang - Urbana IL, US
Tak M. Mak - Union City CA, US
Quan Shi - Beaverton OR, US
Kee Sup Kim - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G01R 31/28

714724

In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.

7523371, Apr 21, 2009

Sep 2, 2005

11/218979

Subhasish Mitra - Folsom CA, US
Ming Zhang - Urbana IL, US
Kee Sup Kim - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G01R 31/28
G06F 7/02
G06F 13/00

714729, 714819

In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable circuit, coupled to the combinational logic circuit, to generate a system bistable signal in response to at least the data input signal; a shadow bistable circuit, coupled to the delay element, to generate a shadow bistable signal in response to at least the delayed data input signal. Further, the apparatus is provided with an output joining circuit, coupled to the system and the shadow bistable circuits, to provide a data output signal in response to the system and the shadow bistable signals.

7574640, Aug 11, 2009

Sep 5, 2003

10/656013

Subhasish Mitra - Rancho Cordova CA, US
Kee Sup Kim - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G01R 31/28

714726

A compactor has a reduced number of outputs and the ability to handle a higher number of errors and unknown logic values. The procedure for designing the matrix and the resulting compactor involves determining the number of unknown logic values that may be encountered and adding columns to the compactor matrix based on the number of errors. Basically, the number of possible combinations of scan in lines is determined. Then, additional columns are added for each possible combination of scan in lines. The number of columns that are added for each combination of scan in lines is equal to the number of errors plus one in one embodiment.