Jun Li

6404927, Jun 11, 2002

Mar 15, 1999

09/268277

Jun Li - Fremont CA
Iskender Agi - San Mateo CA

Exar Corporation - Fremont CA

G06K 936

382232, 382245, 358539

A simple, cost-effective compression circuit which compress raw color data without interpolation. Control points common to all the colors in a line are generated each time one of the colors exceeds the color change threshold. The change in the other color is recorded at the same time even though it doesnt exceed the minimum change threshold.

6548995, Apr 15, 2003

Jan 17, 2002

10/052278

Jun Li - Foster City CA

Silicon Storage Technology, Inc. - Sunnyvale CA

G05F 316

323314, 327537, 327543

A high speed bias voltage generating circuit for use with semiconductor devices. The bias voltage generating circuit includes three circuits or circuit portions and which cooperatively control the output voltage and current of the circuit. The standby circuit is active during a standby mode. The standby circuit provides. a stable standby voltage Vout for the circuit , and generates substantially no current in standby mode. The bias circuit is active during a bias mode and provides a stable bias voltage Vout for the circuit. The boost circuit is active during the transition from standby mode to bias mode, and is effective to quickly lower or âpull downâ the output voltage from Vout to Vout.

6721929, Apr 13, 2004

May 11, 2001

09/854146

Jun Li - San Jose CA
Hong Zhao - Fremont CA

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 6, 716 4, 716 5

A variable current source model accurately determines timing delays for designs of circuits implemented in integrated circuits. A design for an integrated circuit specifies a resistive-capacitive (âRCâ) network. The RC network couples a driving point and a receiving point, and a circuit specified in the design, drives the RC network at the driving point. The variable current source model determines driving currents for the circuit at the driving point based on the RC network and a characterization model of the circuit. A timing delay between the driving point and the receiving point is determined by simulating the drive of the RC network with the driving current at the driving point.

6831017, Dec 14, 2004

Apr 5, 2002

10/117866

Jun Li - Sunnyvale CA
Alan M. Cassell - San Jose CA
Jie Han - Cupertino CA

Integrated Nanosystems, Inc. - Los Gatos CA

H01L 21311

438694, 438486

Nanowire devices may be provided that are based on carbon nanotubes or single-crystal semiconductor nanowires. The nanowire devices may be formed on a substrate. Catalyst sites may be formed on the substrate. The catalyst sites may be formed using lithography, thin metal layers that form individual catalyst sites when heated, collapsible porous catalyst-filled microscopic spheres, microscopic spheres that serve as masks for catalyst deposition, electrochemical deposition techniques, and catalyst inks. Nanowires may be grown from the catalyst sites.

6861103, Mar 1, 2005

Feb 7, 2003

10/360443

Ying Chih Chang - Atherton CA, US
Jun Li - Irvine CA, US
Xiaoru Chen - San Diego CA, US

The Regents of the University of California - Oakland CA

C08F002/46

427522, 526220, 5263031, 526304, 5263171, 526346, 42725511, 42725514, 427487, 427593

Nitroxide mediated free radical polymerization of vaporized vinyl monomers, including acrylic acid (AAc), styrene (St), N-2-(hydroxypropyl)methacrylamide (HPMA) and N-isopropyl acrylamide (NIPAAm), on silicon wafers is demonstrated. FTIR, ellipsometry and contact angle goniometry were used to characterize the chemical structures, thickness and hydrophilicity of the films. The growth of film is linearly proportional to its reaction time, leading to the easy and exact control of polymer film thickness from nanometers to submicrons. The capability of polymerizing various monomers allows us to fabricate various functional polymer brushes. The reversible thermo-responsiveness of a 200 nm thick grafted poly(NIPAAm) film in aqueous solution is demonstrated with over 50% change in thickness at its lower critical solution temperature. A tri-block copolymer of poly(AAc)-b-polySt-b-poly(HPMA) is successfully synthesized, proving the renewability of TEMPO-mediated polymerization at vapor phase. Surface polymer composition and morphology is thus controlled at nanoscale by utilizing vapor phase surface-initiated controlled polymerization.

7073140, Jul 4, 2006

Aug 29, 2003

10/651617

Jun Li - San Jose CA, US
Athanasius Spyrou - Sunnyvale CA, US
Hong Zhao - Fremont CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/90

716 4

Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ration of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.

7094679, Aug 22, 2006

Mar 11, 2003

10/390254

Jun Li - Sunnyvale CA, US
Meyya Meyyappan - San Jose CA, US

The United States of America as represented by the Administrator of the National Aeronautics and Space Administration - Washington DC

H01L 21/4763
H01L 21/302

438618, 438691, 438800, 438626

Method and system for fabricating an electrical interconnect capable of supporting very high current densities (10–10Amps/cm), using an array of one or more carbon nanotubes (CNTs). The CNT array is grown in a selected spaced apart pattern, preferably with multi-wall CNTs, and a selected insulating material, such as SiOor SiN, is deposited using CVD to encapsulate each CNT in the array. An exposed surface of the insulating material is planarized to provide one or more exposed electrical contacts for one or more CNTs.

7109581, Sep 19, 2006

Aug 24, 2004

10/925824

Carlos Dangelo - Los Gatos CA, US
Meyya Meyyappan - San Jose CA, US
Jun Li - Sunnyvale CA, US

Nanoconduction, Inc. - Sunnyvale CA

H01L 23/34

257720, 257E23101, 257E23105, 438122, 977742, 977762

Heat sink structures employing carbon nanotube or nanowire arrays to reduce the thermal interface resistance between an integrated circuit chip and the heat sink are disclosed. Carbon nanotube arrays are combined with a thermally conductive metal filler disposed between the nanotubes. This structure produces a thermal interface with high axial and lateral thermal conductivities.